599 lines
22 KiB
C
599 lines
22 KiB
C
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/**
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******************************************************************************
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* @file stm32f4xx_hal_pwr.c
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* @author MCD Application Team
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* @brief PWR HAL module driver.
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* This file provides firmware functions to manage the following
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* functionalities of the Power Controller (PWR) peripheral:
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* + Initialization and de-initialization functions
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* + Peripheral Control functions
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*
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2017 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file in
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* the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f4xx_hal.h"
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/** @addtogroup STM32F4xx_HAL_Driver
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* @{
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*/
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/** @defgroup PWR PWR
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* @brief PWR HAL module driver
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* @{
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*/
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#ifdef HAL_PWR_MODULE_ENABLED
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/** @addtogroup PWR_Private_Constants
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* @{
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*/
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/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
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* @{
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*/
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#define PVD_MODE_IT 0x00010000U
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#define PVD_MODE_EVT 0x00020000U
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#define PVD_RISING_EDGE 0x00000001U
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#define PVD_FALLING_EDGE 0x00000002U
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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/* Private functions ---------------------------------------------------------*/
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/** @defgroup PWR_Exported_Functions PWR Exported Functions
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* @{
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*/
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/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
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* @brief Initialization and de-initialization functions
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*
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@verbatim
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===============================================================================
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##### Initialization and de-initialization functions #####
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===============================================================================
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[..]
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After reset, the backup domain (RTC registers, RTC backup data
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registers and backup SRAM) is protected against possible unwanted
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write accesses.
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To enable access to the RTC Domain and RTC registers, proceed as follows:
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(+) Enable the Power Controller (PWR) APB1 interface clock using the
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__HAL_RCC_PWR_CLK_ENABLE() macro.
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(+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
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@endverbatim
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* @{
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*/
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/**
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* @brief Deinitializes the HAL PWR peripheral registers to their default reset values.
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* @retval None
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*/
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void HAL_PWR_DeInit(void)
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{
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__HAL_RCC_PWR_FORCE_RESET();
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__HAL_RCC_PWR_RELEASE_RESET();
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}
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/**
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* @brief Enables access to the backup domain (RTC registers, RTC
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* backup data registers and backup SRAM).
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* @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
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* Backup Domain Access should be kept enabled.
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* @note The following sequence is required to bypass the delay between
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* DBP bit programming and the effective enabling of the backup domain.
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* Please check the Errata Sheet for more details under "Possible delay
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* in backup domain protection disabling/enabling after programming the
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* DBP bit" section.
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* @retval None
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*/
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void HAL_PWR_EnableBkUpAccess(void)
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{
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__IO uint32_t dummyread;
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*(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE;
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dummyread = PWR->CR;
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UNUSED(dummyread);
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}
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/**
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* @brief Disables access to the backup domain (RTC registers, RTC
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* backup data registers and backup SRAM).
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* @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
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* Backup Domain Access should be kept enabled.
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* @note The following sequence is required to bypass the delay between
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* DBP bit programming and the effective disabling of the backup domain.
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* Please check the Errata Sheet for more details under "Possible delay
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* in backup domain protection disabling/enabling after programming the
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* DBP bit" section.
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* @retval None
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*/
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void HAL_PWR_DisableBkUpAccess(void)
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{
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__IO uint32_t dummyread;
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*(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE;
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dummyread = PWR->CR;
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UNUSED(dummyread);
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}
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/**
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* @}
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*/
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/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
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* @brief Low Power modes configuration functions
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*
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@verbatim
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===============================================================================
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##### Peripheral Control functions #####
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===============================================================================
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*** PVD configuration ***
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=========================
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[..]
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(+) The PVD is used to monitor the VDD power supply by comparing it to a
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threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
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(+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
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than the PVD threshold. This event is internally connected to the EXTI
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line16 and can generate an interrupt if enabled. This is done through
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__HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
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(+) The PVD is stopped in Standby mode.
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*** Wake-up pin configuration ***
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================================
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[..]
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(+) Wake-up pin is used to wake up the system from Standby mode. This pin is
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forced in input pull-down configuration and is active on rising edges.
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(+) There is one Wake-up pin: Wake-up Pin 1 on PA.00.
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(++) For STM32F446xx there are two Wake-Up pins: Pin1 on PA.00 and Pin2 on PC.13
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(++) For STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx there are three Wake-Up pins: Pin1 on PA.00, Pin2 on PC.00 and Pin3 on PC.01
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*** Low Power modes configuration ***
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=====================================
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[..]
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The devices feature 3 low-power modes:
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(+) Sleep mode: Cortex-M4 core stopped, peripherals kept running.
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(+) Stop mode: all clocks are stopped, regulator running, regulator
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in low power mode
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(+) Standby mode: 1.2V domain powered off.
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*** Sleep mode ***
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==================
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[..]
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(+) Entry:
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The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(Regulator, SLEEPEntry)
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functions with
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(++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
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(++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
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(++) PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR: Enter SLEEP mode with WFE instruction and
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no clear of pending event before.
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-@@- The Regulator parameter is not used for the STM32F4 family
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and is kept as parameter just to maintain compatibility with the
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lower power families (STM32L).
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(+) Exit:
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Any peripheral interrupt acknowledged by the nested vectored interrupt
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controller (NVIC) can wake up the device from Sleep mode.
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*** Stop mode ***
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=================
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[..]
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In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,
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and the HSE RC oscillators are disabled. Internal SRAM and register contents
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are preserved.
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The voltage regulator can be configured either in normal or low-power mode.
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To minimize the consumption In Stop mode, FLASH can be powered off before
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entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function.
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It can be switched on again by software after exiting the Stop mode using
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the HAL_PWREx_DisableFlashPowerDown() function.
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(+) Entry:
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The Stop mode is entered using the HAL_PWR_EnterSTOPMode(Regulator, STOPEntry)
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function with:
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(++) Regulator:
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(+++) Main regulator ON.
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(+++) Low Power regulator ON.
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(++) STOPEntry:
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(+++) PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction.
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(+++) PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction and
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clear of pending events before.
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(+++) PWR_STOPENTRY_WFE_NO_EVT_CLEAR : Enter STOP mode with WFE instruction and
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no clear of pending event before.
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(+) Exit:
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Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
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*** Standby mode ***
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====================
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[..]
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(+)
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The Standby mode allows to achieve the lowest power consumption. It is based
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on the Cortex-M4 deep sleep mode, with the voltage regulator disabled.
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The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and
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the HSE oscillator are also switched off. SRAM and register contents are lost
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except for the RTC registers, RTC backup registers, backup SRAM and Standby
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circuitry.
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The voltage regulator is OFF.
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(++) Entry:
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(+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
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(++) Exit:
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(+++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wake-up,
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tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
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*** Auto-wake-up (AWU) from low-power mode ***
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=============================================
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[..]
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(+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
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Wake-up event, a tamper event or a time-stamp event, without depending on
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an external interrupt (Auto-wake-up mode).
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(+) RTC auto-wake-up (AWU) from the Stop and Standby modes
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(++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
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configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
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(++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
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is necessary to configure the RTC to detect the tamper or time stamp event using the
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HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
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(++) To wake up from the Stop mode with an RTC Wake-up event, it is necessary to
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configure the RTC to generate the RTC Wake-up event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
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@endverbatim
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* @{
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*/
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/**
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* @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
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* @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration
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* information for the PVD.
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* @note Refer to the electrical characteristics of your device datasheet for
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* more details about the voltage threshold corresponding to each
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* detection level.
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* @retval None
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*/
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void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
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{
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/* Check the parameters */
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assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
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assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
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/* Set PLS[7:5] bits according to PVDLevel value */
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MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);
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/* Clear any previous config. Keep it clear if no event or IT mode is selected */
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__HAL_PWR_PVD_EXTI_DISABLE_EVENT();
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__HAL_PWR_PVD_EXTI_DISABLE_IT();
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__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
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__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
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/* Configure interrupt mode */
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if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
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{
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__HAL_PWR_PVD_EXTI_ENABLE_IT();
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}
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/* Configure event mode */
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if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
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{
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__HAL_PWR_PVD_EXTI_ENABLE_EVENT();
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}
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/* Configure the edge */
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if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
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{
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__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
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}
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if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
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{
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__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
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}
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}
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/**
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* @brief Enables the Power Voltage Detector(PVD).
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* @retval None
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*/
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void HAL_PWR_EnablePVD(void)
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{
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*(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE;
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}
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/**
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* @brief Disables the Power Voltage Detector(PVD).
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* @retval None
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*/
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void HAL_PWR_DisablePVD(void)
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{
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*(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE;
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}
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/**
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* @brief Enables the Wake-up PINx functionality.
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* @param WakeUpPinx Specifies the Power Wake-Up pin to enable.
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* This parameter can be one of the following values:
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* @arg PWR_WAKEUP_PIN1
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* @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412xx/STM32F413xx/STM32F423xx devices
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* @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx devices
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* @retval None
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*/
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void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
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{
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/* Check the parameter */
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assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
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/* Enable the wake up pin */
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SET_BIT(PWR->CSR, WakeUpPinx);
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}
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/**
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* @brief Disables the Wake-up PINx functionality.
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* @param WakeUpPinx Specifies the Power Wake-Up pin to disable.
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* This parameter can be one of the following values:
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* @arg PWR_WAKEUP_PIN1
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* @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412xx/STM32F413xx/STM32F423xx devices
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* @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx devices
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* @retval None
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*/
|
||
|
|
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
|
||
|
|
{
|
||
|
|
/* Check the parameter */
|
||
|
|
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
|
||
|
|
|
||
|
|
/* Disable the wake up pin */
|
||
|
|
CLEAR_BIT(PWR->CSR, WakeUpPinx);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Enters Sleep mode.
|
||
|
|
*
|
||
|
|
* @note In Sleep mode, all I/O pins keep the same state as in Run mode.
|
||
|
|
*
|
||
|
|
* @note In Sleep mode, the systick is stopped to avoid exit from this mode with
|
||
|
|
* systick interrupt when used as time base for Timeout
|
||
|
|
*
|
||
|
|
* @param Regulator Specifies the regulator state in SLEEP mode.
|
||
|
|
* This parameter can be one of the following values:
|
||
|
|
* @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
|
||
|
|
* @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
|
||
|
|
* @note This parameter is not used for the STM32F4 family and is kept as parameter
|
||
|
|
* just to maintain compatibility with the lower power families.
|
||
|
|
* @param SLEEPEntry Specifies if SLEEP mode in entered with WFI or WFE instruction.
|
||
|
|
* This parameter can be one of the following values:
|
||
|
|
* @arg PWR_SLEEPENTRY_WFI : Enter SLEEP mode with WFI instruction
|
||
|
|
* @arg PWR_SLEEPENTRY_WFE : Enter SLEEP mode with WFE instruction and
|
||
|
|
* clear of pending events before.
|
||
|
|
* @arg PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR : Enter SLEEP mode with WFE instruction and
|
||
|
|
* no clear of pending event before.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
|
||
|
|
{
|
||
|
|
/* Prevent unused argument(s) compilation warning */
|
||
|
|
UNUSED(Regulator);
|
||
|
|
|
||
|
|
/* Check the parameters */
|
||
|
|
assert_param(IS_PWR_REGULATOR(Regulator));
|
||
|
|
assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
|
||
|
|
|
||
|
|
/* Clear SLEEPDEEP bit of Cortex System Control Register */
|
||
|
|
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
||
|
|
|
||
|
|
/* Select SLEEP mode entry -------------------------------------------------*/
|
||
|
|
if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
|
||
|
|
{
|
||
|
|
/* Request Wait For Interrupt */
|
||
|
|
__WFI();
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
if(SLEEPEntry != PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR)
|
||
|
|
{
|
||
|
|
/* Clear all pending event */
|
||
|
|
__SEV();
|
||
|
|
__WFE();
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Request Wait For Event */
|
||
|
|
__WFE();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Enters Stop mode.
|
||
|
|
* @note In Stop mode, all I/O pins keep the same state as in Run mode.
|
||
|
|
* @note When exiting Stop mode by issuing an interrupt or a wake-up event,
|
||
|
|
* the HSI RC oscillator is selected as system clock.
|
||
|
|
* @note When the voltage regulator operates in low power mode, an additional
|
||
|
|
* startup delay is incurred when waking up from Stop mode.
|
||
|
|
* By keeping the internal regulator ON during Stop mode, the consumption
|
||
|
|
* is higher although the startup time is reduced.
|
||
|
|
* @param Regulator Specifies the regulator state in Stop mode.
|
||
|
|
* This parameter can be one of the following values:
|
||
|
|
* @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
|
||
|
|
* @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
|
||
|
|
* @param STOPEntry Specifies if Stop mode in entered with WFI or WFE instruction.
|
||
|
|
* This parameter can be one of the following values:
|
||
|
|
* @arg PWR_STOPENTRY_WFI : Enter Stop mode with WFI instruction
|
||
|
|
* @arg PWR_STOPENTRY_WFE : Enter Stop mode with WFE instruction and
|
||
|
|
* clear of pending events before.
|
||
|
|
* @arg PWR_STOPENTRY_WFE_NO_EVT_CLEAR : Enter STOP mode with WFE instruction and
|
||
|
|
* no clear of pending event before.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
|
||
|
|
{
|
||
|
|
/* Check the parameters */
|
||
|
|
assert_param(IS_PWR_REGULATOR(Regulator));
|
||
|
|
assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
|
||
|
|
|
||
|
|
/* Select the regulator state in Stop mode: Set PDDS and LPDS bits according to PWR_Regulator value */
|
||
|
|
MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS), Regulator);
|
||
|
|
|
||
|
|
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
||
|
|
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
||
|
|
|
||
|
|
/* Select Stop mode entry --------------------------------------------------*/
|
||
|
|
if(STOPEntry == PWR_STOPENTRY_WFI)
|
||
|
|
{
|
||
|
|
/* Request Wait For Interrupt */
|
||
|
|
__WFI();
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
if(STOPEntry != PWR_STOPENTRY_WFE_NO_EVT_CLEAR)
|
||
|
|
{
|
||
|
|
/* Clear all pending event */
|
||
|
|
__SEV();
|
||
|
|
__WFE();
|
||
|
|
}
|
||
|
|
/* Request Wait For Event */
|
||
|
|
__WFE();
|
||
|
|
}
|
||
|
|
/* Reset SLEEPDEEP bit of Cortex System Control Register */
|
||
|
|
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Enters Standby mode.
|
||
|
|
* @note In Standby mode, all I/O pins are high impedance except for:
|
||
|
|
* - Reset pad (still available)
|
||
|
|
* - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC
|
||
|
|
* Alarm out, or RTC clock calibration out.
|
||
|
|
* - RTC_AF2 pin (PI8) if configured for tamper or time-stamp.
|
||
|
|
* - WKUP pin 1 (PA0) if enabled.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void HAL_PWR_EnterSTANDBYMode(void)
|
||
|
|
{
|
||
|
|
/* Select Standby mode */
|
||
|
|
SET_BIT(PWR->CR, PWR_CR_PDDS);
|
||
|
|
|
||
|
|
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
||
|
|
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
||
|
|
|
||
|
|
/* This option is used to ensure that store operations are completed */
|
||
|
|
#if defined ( __CC_ARM)
|
||
|
|
__force_stores();
|
||
|
|
#endif
|
||
|
|
/* Request Wait For Interrupt */
|
||
|
|
__WFI();
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief This function handles the PWR PVD interrupt request.
|
||
|
|
* @note This API should be called under the PVD_IRQHandler().
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void HAL_PWR_PVD_IRQHandler(void)
|
||
|
|
{
|
||
|
|
/* Check PWR Exti flag */
|
||
|
|
if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
|
||
|
|
{
|
||
|
|
/* PWR PVD interrupt user callback */
|
||
|
|
HAL_PWR_PVDCallback();
|
||
|
|
|
||
|
|
/* Clear PWR Exti pending bit */
|
||
|
|
__HAL_PWR_PVD_EXTI_CLEAR_FLAG();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief PWR PVD interrupt callback
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
__weak void HAL_PWR_PVDCallback(void)
|
||
|
|
{
|
||
|
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
||
|
|
the HAL_PWR_PVDCallback could be implemented in the user file
|
||
|
|
*/
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
|
||
|
|
* @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
|
||
|
|
* re-enters SLEEP mode when an interruption handling is over.
|
||
|
|
* Setting this bit is useful when the processor is expected to run only on
|
||
|
|
* interruptions handling.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void HAL_PWR_EnableSleepOnExit(void)
|
||
|
|
{
|
||
|
|
/* Set SLEEPONEXIT bit of Cortex System Control Register */
|
||
|
|
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
|
||
|
|
* @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
|
||
|
|
* re-enters SLEEP mode when an interruption handling is over.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void HAL_PWR_DisableSleepOnExit(void)
|
||
|
|
{
|
||
|
|
/* Clear SLEEPONEXIT bit of Cortex System Control Register */
|
||
|
|
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Enables CORTEX M4 SEVONPEND bit.
|
||
|
|
* @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
|
||
|
|
* WFE to wake up when an interrupt moves from inactive to pended.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void HAL_PWR_EnableSEVOnPend(void)
|
||
|
|
{
|
||
|
|
/* Set SEVONPEND bit of Cortex System Control Register */
|
||
|
|
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Disables CORTEX M4 SEVONPEND bit.
|
||
|
|
* @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
|
||
|
|
* WFE to wake up when an interrupt moves from inactive to pended.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void HAL_PWR_DisableSEVOnPend(void)
|
||
|
|
{
|
||
|
|
/* Clear SEVONPEND bit of Cortex System Control Register */
|
||
|
|
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
#endif /* HAL_PWR_MODULE_ENABLED */
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|