311 lines
10 KiB
C
311 lines
10 KiB
C
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/**
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******************************************************************************
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* @file stm32f4xx_hal_sai_ex.c
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* @author MCD Application Team
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* @brief SAI Extension HAL module driver.
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* This file provides firmware functions to manage the following
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* functionalities of SAI extension peripheral:
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* + Extension features functions
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*
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2017 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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@verbatim
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==============================================================================
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##### SAI peripheral extension features #####
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==============================================================================
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[..] Comparing to other previous devices, the SAI interface for STM32F446xx
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devices contains the following additional features :
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(+) Possibility to be clocked from PLLR
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##### How to use this driver #####
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==============================================================================
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[..] This driver provides functions to manage several sources to clock SAI
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@endverbatim
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f4xx_hal.h"
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/** @addtogroup STM32F4xx_HAL_Driver
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* @{
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*/
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/** @defgroup SAIEx SAIEx
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* @brief SAI Extension HAL module driver
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* @{
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*/
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#ifdef HAL_SAI_MODULE_ENABLED
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#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
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defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F413xx) || \
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defined(STM32F423xx)
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/* SAI registers Masks */
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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/* Private functions ---------------------------------------------------------*/
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/** @defgroup SAI_Private_Functions SAI Private Functions
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* @{
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*/
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/**
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* @}
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*/
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/* Exported functions --------------------------------------------------------*/
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/** @defgroup SAIEx_Exported_Functions SAI Extended Exported Functions
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* @{
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*/
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/** @defgroup SAIEx_Exported_Functions_Group1 Extension features functions
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* @brief Extension features functions
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*
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@verbatim
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===============================================================================
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##### Extension features Functions #####
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===============================================================================
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[..]
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This subsection provides a set of functions allowing to manage the possible
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SAI clock sources.
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@endverbatim
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* @{
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*/
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/**
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* @brief Configure SAI Block synchronization mode
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* @param hsai pointer to a SAI_HandleTypeDef structure that contains
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* the configuration information for SAI module.
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* @retval SAI Clock Input
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*/
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void SAI_BlockSynchroConfig(const SAI_HandleTypeDef *hsai)
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{
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uint32_t tmpregisterGCR;
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#if defined(STM32F446xx)
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/* This setting must be done with both audio block (A & B) disabled */
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switch (hsai->Init.SynchroExt)
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{
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case SAI_SYNCEXT_DISABLE :
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tmpregisterGCR = 0U;
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break;
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case SAI_SYNCEXT_OUTBLOCKA_ENABLE :
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tmpregisterGCR = SAI_GCR_SYNCOUT_0;
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break;
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case SAI_SYNCEXT_OUTBLOCKB_ENABLE :
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tmpregisterGCR = SAI_GCR_SYNCOUT_1;
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break;
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default:
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tmpregisterGCR = 0U;
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break;
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}
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if ((hsai->Init.Synchro) == SAI_SYNCHRONOUS_EXT_SAI2)
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{
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tmpregisterGCR |= SAI_GCR_SYNCIN_0;
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}
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if ((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B))
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{
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SAI1->GCR = tmpregisterGCR;
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}
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else
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{
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SAI2->GCR = tmpregisterGCR;
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}
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#endif /* STM32F446xx */
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#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
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defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F413xx) || defined(STM32F423xx)
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/* This setting must be done with both audio block (A & B) disabled */
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switch (hsai->Init.SynchroExt)
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{
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case SAI_SYNCEXT_DISABLE :
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tmpregisterGCR = 0U;
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break;
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case SAI_SYNCEXT_OUTBLOCKA_ENABLE :
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tmpregisterGCR = SAI_GCR_SYNCOUT_0;
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break;
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case SAI_SYNCEXT_OUTBLOCKB_ENABLE :
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tmpregisterGCR = SAI_GCR_SYNCOUT_1;
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break;
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default:
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tmpregisterGCR = 0U;
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break;
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}
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SAI1->GCR = tmpregisterGCR;
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#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F413xx || STM32F423xx */
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}
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/**
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* @brief Get SAI Input Clock based on SAI source clock selection
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* @param hsai pointer to a SAI_HandleTypeDef structure that contains
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* the configuration information for SAI module.
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* @retval SAI Clock Input
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*/
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uint32_t SAI_GetInputClock(const SAI_HandleTypeDef *hsai)
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{
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/* This variable used to store the SAI_CK_x (value in Hz) */
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uint32_t saiclocksource = 0U;
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#if defined(STM32F446xx)
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if ((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B))
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{
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saiclocksource = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI1);
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}
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else /* SAI2_Block_A || SAI2_Block_B*/
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{
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saiclocksource = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI2);
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}
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#endif /* STM32F446xx */
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#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
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defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F413xx) || defined(STM32F423xx)
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uint32_t vcoinput = 0U, tmpreg = 0U;
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/* Check the SAI Block parameters */
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assert_param(IS_SAI_CLK_SOURCE(hsai->Init.ClockSource));
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/* SAI Block clock source selection */
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if (hsai->Instance == SAI1_Block_A)
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{
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__HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(hsai->Init.ClockSource);
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}
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else
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{
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__HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG((uint32_t)(hsai->Init.ClockSource << 2U));
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}
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/* VCO Input Clock value calculation */
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if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
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{
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/* In Case the PLL Source is HSI (Internal Clock) */
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vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
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}
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else
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{
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/* In Case the PLL Source is HSE (External Clock) */
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vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
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}
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#if defined(STM32F413xx) || defined(STM32F423xx)
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/* SAI_CLK_x : SAI Block Clock configuration for different clock sources selected */
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if (hsai->Init.ClockSource == SAI_CLKSOURCE_PLLR)
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{
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/* Configure the PLLI2S division factor */
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/* PLL_VCO Input = PLL_SOURCE/PLLM */
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/* PLL_VCO Output = PLL_VCO Input * PLLN */
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/* SAI_CLK(first level) = PLL_VCO Output/PLLR */
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tmpreg = (RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U;
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saiclocksource = (vcoinput * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U)) / (tmpreg);
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/* SAI_CLK_x = SAI_CLK(first level)/PLLDIVR */
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tmpreg = (((RCC->DCKCFGR & RCC_DCKCFGR_PLLDIVR) >> 8U) + 1U);
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saiclocksource = saiclocksource / (tmpreg);
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}
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else if (hsai->Init.ClockSource == SAI_CLKSOURCE_PLLI2S)
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{
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/* Configure the PLLI2S division factor */
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/* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
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/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
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/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SR */
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tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U;
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saiclocksource = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U)) / (tmpreg);
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/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVR */
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tmpreg = ((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVR) + 1U);
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saiclocksource = saiclocksource / (tmpreg);
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}
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else if (hsai->Init.ClockSource == SAI_CLKSOURCE_HS)
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{
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if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
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{
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/* Get the I2S source clock value */
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saiclocksource = (uint32_t)(HSE_VALUE);
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}
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else
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{
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/* Get the I2S source clock value */
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saiclocksource = (uint32_t)(HSI_VALUE);
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}
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}
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else /* sConfig->ClockSource == SAI_CLKSource_Ext */
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{
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saiclocksource = EXTERNAL_CLOCK_VALUE;
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}
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#else
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/* SAI_CLK_x : SAI Block Clock configuration for different clock sources selected */
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if (hsai->Init.ClockSource == SAI_CLKSOURCE_PLLSAI)
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{
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/* Configure the PLLI2S division factor */
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/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
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/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
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/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
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tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24U;
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saiclocksource = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6U)) / (tmpreg);
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/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
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tmpreg = (((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> 8U) + 1U);
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saiclocksource = saiclocksource / (tmpreg);
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}
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else if (hsai->Init.ClockSource == SAI_CLKSOURCE_PLLI2S)
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{
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/* Configure the PLLI2S division factor */
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/* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
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/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
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/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
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tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24U;
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saiclocksource = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U)) / (tmpreg);
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/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
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tmpreg = ((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) + 1U);
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saiclocksource = saiclocksource / (tmpreg);
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}
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else /* sConfig->ClockSource == SAI_CLKSource_Ext */
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{
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/* Enable the External Clock selection */
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__HAL_RCC_I2S_CONFIG(RCC_I2SCLKSOURCE_EXT);
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saiclocksource = EXTERNAL_CLOCK_VALUE;
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}
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#endif /* STM32F413xx || STM32F423xx */
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#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F413xx || STM32F423xx */
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/* the return result is the value of SAI clock */
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return saiclocksource;
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}
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/**
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* @}
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*/
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/**
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* @}
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*/
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#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F413xx || STM32F423xx */
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#endif /* HAL_SAI_MODULE_ENABLED */
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/**
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* @}
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*/
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/**
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* @}
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*/
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