110 lines
3.5 KiB
Plaintext
110 lines
3.5 KiB
Plaintext
* I2C controller embedded in STMicroelectronics STM32 I2C platform
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Required properties :
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- compatible : Must be one of the following
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- "st,stm32f4-i2c"
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- "st,stm32f7-i2c"
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- reg : Offset and length of the register set for the device
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- interrupts : Must contain the interrupt id for I2C event and then the
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interrupt id for I2C error.
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Optionnaly a wakeup interrupt may be specified.
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- resets: Must contain the phandle to the reset controller.
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- clocks: Must contain the input clock of the I2C instance.
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- A pinctrl state named "default" must be defined to set pins in mode of
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operation for I2C transfer. An optional pinctrl state named "sleep" has to
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be defined as well as to put I2C in low power mode in suspend mode.
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- #address-cells = <1>;
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- #size-cells = <0>;
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Optional properties :
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- clock-frequency : Desired I2C bus clock frequency in Hz. If not specified,
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the default 100 kHz frequency will be used.
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For STM32F4 SoC Standard-mode and Fast-mode are supported, possible values are
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100000 and 400000.
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For STM32F7, STM32H7 and STM32MP1 SoCs, Standard-mode, Fast-mode and Fast-mode
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Plus are supported, possible values are 100000, 400000 and 1000000.
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- i2c-scl-rising-time-ns: I2C SCL Rising time for the board (default: 25)
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For STM32F7, STM32H7 and STM32MP1 only.
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- i2c-scl-falling-time-ns: I2C SCL Falling time for the board (default: 10)
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For STM32F7, STM32H7 and STM32MP1 only.
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I2C Timings are derived from these 2 values
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- st,syscfg-fmp: Use to set Fast Mode Plus bit within SYSCFG when Fast Mode
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Plus speed is selected by slave.
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1st cell : phandle to syscfg
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2nd cell : register offset within SYSCFG
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3rd cell : register bitmask for FMP bit
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For STM32F7, STM32H7 and STM32MP1 only.
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- st,syscfg-fmp-clr: Use to clear Fast Mode Plus bit within SYSCFG when Fast
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Mode Plus speed is selected by slave.
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1st cell: phandle to syscfg
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2nd cell: clear register offset within SYSCFG
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3rd cell: register bitmask for FMP clear bit
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For STM32MP1 family only.
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Example :
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i2c@40005400 {
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compatible = "st,stm32f4-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40005400 0x400>;
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interrupts = <31>,
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<32>;
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resets = <&rcc 277>;
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clocks = <&rcc 0 149>;
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pinctrl-0 = <&i2c1_sda_pin>, <&i2c1_scl_pin>;
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pinctrl-names = "default";
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};
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i2c@40005400 {
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compatible = "st,stm32f7-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40005400 0x400>;
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interrupts = <31>,
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<32>;
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resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
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clocks = <&rcc 1 CLK_I2C1>;
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pinctrl-0 = <&i2c1_sda_pin>, <&i2c1_scl_pin>;
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pinctrl-1 = <&i2c1_sda_pin_sleep>, <&i2c1_scl_pin_sleep>;
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pinctrl-names = "default", "sleep";
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st,syscfg-fmp = <&syscfg 0x4 0x1>;
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st,syscfg-fmp-clr = <&syscfg 0x44 0x1>;
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};
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i2c@40013000 {
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compatible = "st,stm32f7-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40013000 0x400>;
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interrupt-names = "event", "error", "wakeup";
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interrupts-extended = <&intc GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
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<&intc GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
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<&exti 22 1>;
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clocks = <&rcc I2C2_K>;
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resets = <&rcc I2C2_R>;
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st,syscfg-fmp = <&syscfg 0x4 0x2>;
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st,syscfg-fmp-clr = <&syscfg 0x44 0x2>;
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};
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* I2C Devices
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An I2C device connected onto STM32 I2C controller must use a format described by
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i2c.txt file.
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Required properties :
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- compatible
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Device driver compatible name
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- reg
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I2C slave addresses (see i2c.txt for more details)
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Optional properties :
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i2c@40013000 {
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camera@3c {
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compatible = "ovti,ov5640";
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reg = <0x3c>;
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};
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};
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