226 lines
4.5 KiB
C
226 lines
4.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2014 - 2018 Xilinx, Inc.
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* Michal Simek <michal.simek@xilinx.com>
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*/
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#include <common.h>
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#include <fdtdec.h>
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#include <init.h>
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#include <malloc.h>
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#include <time.h>
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/sys_proto.h>
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#include <dm/device.h>
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#include <dm/uclass.h>
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#include <versalpl.h>
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#include <linux/sizes.h>
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_FPGA_VERSALPL)
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static xilinx_desc versalpl = XILINX_VERSAL_DESC;
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#endif
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int board_init(void)
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{
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printf("EL Level:\tEL%d\n", current_el());
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#if defined(CONFIG_FPGA_VERSALPL)
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fpga_init();
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fpga_add(fpga_xilinx, &versalpl);
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#endif
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return 0;
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}
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int board_early_init_r(void)
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{
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u32 val;
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if (current_el() != 3)
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return 0;
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debug("iou_switch ctrl div0 %x\n",
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readl(&crlapb_base->iou_switch_ctrl));
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writel(IOU_SWITCH_CTRL_CLKACT_BIT |
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(CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
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&crlapb_base->iou_switch_ctrl);
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/* Global timer init - Program time stamp reference clk */
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val = readl(&crlapb_base->timestamp_ref_ctrl);
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val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
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writel(val, &crlapb_base->timestamp_ref_ctrl);
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debug("ref ctrl 0x%x\n",
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readl(&crlapb_base->timestamp_ref_ctrl));
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/* Clear reset of timestamp reg */
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writel(0, &crlapb_base->rst_timestamp);
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/*
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* Program freq register in System counter and
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* enable system counter.
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*/
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writel(COUNTER_FREQUENCY,
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&iou_scntr_secure->base_frequency_id_register);
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debug("counter val 0x%x\n",
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readl(&iou_scntr_secure->base_frequency_id_register));
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writel(IOU_SCNTRS_CONTROL_EN,
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&iou_scntr_secure->counter_control_register);
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debug("scntrs control 0x%x\n",
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readl(&iou_scntr_secure->counter_control_register));
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debug("timer 0x%llx\n", get_ticks());
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debug("timer 0x%llx\n", get_ticks());
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return 0;
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}
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int board_late_init(void)
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{
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u32 reg = 0;
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u8 bootmode;
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struct udevice *dev;
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int bootseq = -1;
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int bootseq_len = 0;
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int env_targets_len = 0;
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const char *mode;
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char *new_targets;
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char *env_targets;
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ulong initrd_hi;
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if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
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debug("Saved variables - Skipping\n");
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return 0;
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}
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reg = readl(&crp_base->boot_mode_usr);
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if (reg >> BOOT_MODE_ALT_SHIFT)
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reg >>= BOOT_MODE_ALT_SHIFT;
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bootmode = reg & BOOT_MODES_MASK;
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puts("Bootmode: ");
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switch (bootmode) {
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case USB_MODE:
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puts("USB_MODE\n");
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mode = "dfu_usb";
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break;
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case JTAG_MODE:
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puts("JTAG_MODE\n");
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mode = "jtag pxe dhcp";
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break;
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case QSPI_MODE_24BIT:
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puts("QSPI_MODE_24\n");
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mode = "xspi0";
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break;
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case QSPI_MODE_32BIT:
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puts("QSPI_MODE_32\n");
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mode = "xspi0";
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break;
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case OSPI_MODE:
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puts("OSPI_MODE\n");
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mode = "xspi0";
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break;
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case EMMC_MODE:
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puts("EMMC_MODE\n");
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mode = "mmc0";
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break;
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case SD_MODE:
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puts("SD_MODE\n");
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if (uclass_get_device_by_name(UCLASS_MMC,
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"sdhci@f1040000", &dev)) {
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puts("Boot from SD0 but without SD0 enabled!\n");
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return -1;
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}
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debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
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mode = "mmc";
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bootseq = dev->seq;
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break;
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case SD1_LSHFT_MODE:
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puts("LVL_SHFT_");
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/* fall through */
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case SD_MODE1:
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puts("SD_MODE1\n");
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if (uclass_get_device_by_name(UCLASS_MMC,
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"sdhci@f1050000", &dev)) {
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puts("Boot from SD1 but without SD1 enabled!\n");
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return -1;
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}
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debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
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mode = "mmc";
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bootseq = dev->seq;
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break;
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default:
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mode = "";
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printf("Invalid Boot Mode:0x%x\n", bootmode);
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break;
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}
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if (bootseq >= 0) {
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bootseq_len = snprintf(NULL, 0, "%i", bootseq);
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debug("Bootseq len: %x\n", bootseq_len);
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}
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/*
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* One terminating char + one byte for space between mode
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* and default boot_targets
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*/
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env_targets = env_get("boot_targets");
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if (env_targets)
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env_targets_len = strlen(env_targets);
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new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
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bootseq_len);
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if (!new_targets)
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return -ENOMEM;
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if (bootseq >= 0)
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sprintf(new_targets, "%s%x %s", mode, bootseq,
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env_targets ? env_targets : "");
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else
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sprintf(new_targets, "%s %s", mode,
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env_targets ? env_targets : "");
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env_set("boot_targets", new_targets);
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initrd_hi = gd->start_addr_sp - CONFIG_STACK_SIZE;
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initrd_hi = round_down(initrd_hi, SZ_16M);
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env_set_addr("initrd_high", (void *)initrd_hi);
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return 0;
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}
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int dram_init_banksize(void)
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{
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int ret;
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ret = fdtdec_setup_memory_banksize();
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if (ret)
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return ret;
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mem_map_fill();
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return 0;
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}
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int dram_init(void)
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{
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if (fdtdec_setup_mem_size_base() != 0)
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return -EINVAL;
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return 0;
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}
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void reset_cpu(ulong addr)
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{
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}
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