251 lines
5.4 KiB
C
251 lines
5.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2012, Stefano Babic <sbabic@denx.de>
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*
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* Based on flea3.c and mx35pdk.c
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <linux/errno.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/iomux-mx35.h>
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#include <i2c.h>
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#include <power/pmic.h>
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#include <fsl_pmic.h>
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#include <mc13892.h>
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#include <mmc.h>
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#include <fsl_esdhc_imx.h>
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#include <linux/types.h>
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#include <asm/gpio.h>
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#include <asm/arch/sys_proto.h>
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#include <netdev.h>
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#include <spl.h>
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#define CCM_CCMR_CONFIG 0x003F4208
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#define ESDCTL_DDR2_CONFIG 0x007FFC3F
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/* For MMC */
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#define GPIO_MMC_CD 7
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#define GPIO_MMC_WP 8
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DECLARE_GLOBAL_DATA_PTR;
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
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PHYS_SDRAM_1_SIZE);
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return 0;
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}
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static void board_setup_sdram(void)
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{
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struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
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/* Initialize with default values both CSD0/1 */
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writel(0x2000, &esdc->esdctl0);
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writel(0x2000, &esdc->esdctl1);
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mx3_setup_sdram_bank(CSD0_BASE_ADDR, ESDCTL_DDR2_CONFIG,
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13, 10, 2, 0x8080);
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}
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static void setup_iomux_fec(void)
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{
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static const iomux_v3_cfg_t fec_pads[] = {
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MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
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MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
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MX35_PAD_FEC_RX_DV__FEC_RX_DV,
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MX35_PAD_FEC_COL__FEC_COL,
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MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
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MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
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MX35_PAD_FEC_TX_EN__FEC_TX_EN,
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MX35_PAD_FEC_MDC__FEC_MDC,
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MX35_PAD_FEC_MDIO__FEC_MDIO,
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MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
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MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
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MX35_PAD_FEC_CRS__FEC_CRS,
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MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
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MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
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MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
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MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
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MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
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MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
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};
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/* setup pins for FEC */
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imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
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}
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int woodburn_init(void)
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{
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struct ccm_regs *ccm =
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(struct ccm_regs *)IMX_CCM_BASE;
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/* initialize PLL and clock configuration */
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writel(CCM_CCMR_CONFIG, &ccm->ccmr);
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/* Set-up RAM */
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board_setup_sdram();
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/* enable clocks */
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writel(readl(&ccm->cgr0) |
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MXC_CCM_CGR0_EMI_MASK |
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MXC_CCM_CGR0_EDIO_MASK |
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MXC_CCM_CGR0_EPIT1_MASK,
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&ccm->cgr0);
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writel(readl(&ccm->cgr1) |
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MXC_CCM_CGR1_FEC_MASK |
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MXC_CCM_CGR1_GPIO1_MASK |
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MXC_CCM_CGR1_GPIO2_MASK |
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MXC_CCM_CGR1_GPIO3_MASK |
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MXC_CCM_CGR1_I2C1_MASK |
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MXC_CCM_CGR1_I2C2_MASK |
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MXC_CCM_CGR1_I2C3_MASK,
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&ccm->cgr1);
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/* Set-up NAND */
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__raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
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/* Set pinmux for the required peripherals */
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setup_iomux_fec();
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/* setup GPIO1_4 FEC_ENABLE signal */
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imx_iomux_v3_setup_pad(MX35_PAD_SCKR__GPIO1_4);
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gpio_direction_output(4, 1);
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imx_iomux_v3_setup_pad(MX35_PAD_HCKT__GPIO1_9);
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gpio_direction_output(9, 1);
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return 0;
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}
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#if defined(CONFIG_SPL_BUILD)
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void board_init_f(ulong dummy)
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{
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/* Set the stack pointer. */
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asm volatile("mov sp, %0\n" : : "r"(CONFIG_SPL_STACK));
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/* Initialize MUX and SDRAM */
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woodburn_init();
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/* Clear the BSS. */
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memset(__bss_start, 0, __bss_end - __bss_start);
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preloader_console_init();
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timer_init();
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board_init_r(NULL, 0);
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}
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void spl_board_init(void)
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{
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}
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#endif
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/* Booting from NOR in external mode */
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int board_early_init_f(void)
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{
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return woodburn_init();
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}
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int board_init(void)
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{
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struct pmic *p;
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u32 val;
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int ret;
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/* address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
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ret = pmic_init(I2C_PMIC);
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if (ret)
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return ret;
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p = pmic_get("FSL_PMIC");
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/*
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* Set switchers in Auto in NORMAL mode & STANDBY mode
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* Setup the switcher mode for SW1 & SW2
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*/
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pmic_reg_read(p, REG_SW_4, &val);
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val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
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(SWMODE_MASK << SWMODE2_SHIFT)));
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val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
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(SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
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/* Set SWILIMB */
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val |= (1 << 22);
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pmic_reg_write(p, REG_SW_4, val);
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/* Setup the switcher mode for SW3 & SW4 */
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pmic_reg_read(p, REG_SW_5, &val);
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val &= ~((SWMODE_MASK << SWMODE4_SHIFT) |
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(SWMODE_MASK << SWMODE3_SHIFT));
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val |= (SWMODE_AUTO_AUTO << SWMODE4_SHIFT) |
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(SWMODE_AUTO_AUTO << SWMODE3_SHIFT);
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pmic_reg_write(p, REG_SW_5, val);
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/* Set VGEN1 to 3.15V */
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pmic_reg_read(p, REG_SETTING_0, &val);
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val &= ~(VGEN1_MASK);
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val |= VGEN1_3_15;
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pmic_reg_write(p, REG_SETTING_0, val);
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pmic_reg_read(p, REG_MODE_0, &val);
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val |= VGEN1EN;
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pmic_reg_write(p, REG_MODE_0, val);
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udelay(2000);
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return 0;
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}
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#if defined(CONFIG_FSL_ESDHC_IMX)
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struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR};
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int board_mmc_init(bd_t *bis)
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{
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static const iomux_v3_cfg_t sdhc1_pads[] = {
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MX35_PAD_SD1_CMD__ESDHC1_CMD,
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MX35_PAD_SD1_CLK__ESDHC1_CLK,
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MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
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MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
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MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
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MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
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};
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/* configure pins for SDHC1 only */
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imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads));
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/* MMC Card Detect on GPIO1_7 */
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imx_iomux_v3_setup_pad(MX35_PAD_SCKT__GPIO1_7);
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gpio_direction_input(GPIO_MMC_CD);
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/* MMC Write Protection on GPIO1_8 */
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imx_iomux_v3_setup_pad(MX35_PAD_FST__GPIO1_8);
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gpio_direction_input(GPIO_MMC_WP);
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esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
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return fsl_esdhc_initialize(bis, &esdhc_cfg);
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}
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int board_mmc_getcd(struct mmc *mmc)
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{
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return !gpio_get_value(GPIO_MMC_CD);
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}
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#endif
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u32 get_board_rev(void)
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{
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int rev = 0;
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return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
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}
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