160 lines
3.9 KiB
C
160 lines
3.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Synopsys, Inc. All rights reserved.
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*/
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#include <common.h>
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#include <malloc.h>
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#include <dwmmc.h>
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#include <linux/libfdt.h>
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#include <fdtdec.h>
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#include <asm/arcregs.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define SYSCON_BASE 0xf000a000
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#define AHBCKDIV (void *)(SYSCON_BASE + 0x04)
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#define APBCKDIV (void *)(SYSCON_BASE + 0x08)
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#define APBCKEN (void *)(SYSCON_BASE + 0x0C)
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#define RESET_REG (void *)(SYSCON_BASE + 0x18)
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#define CLKSEL (void *)(SYSCON_BASE + 0x24)
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#define CLKSTAT (void *)(SYSCON_BASE + 0x28)
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#define PLLCON (void *)(SYSCON_BASE + 0x2C)
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#define APBCKSEL (void *)(SYSCON_BASE + 0x30)
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#define AHBCKEN (void *)(SYSCON_BASE + 0x34)
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#define USBPHY_PLL (void *)(SYSCON_BASE + 0x78)
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#define USBCFG (void *)(SYSCON_BASE + 0x7c)
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#define PLL_MASK_0 0xffcfffff
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#define PLL_MASK_1 0xffcfff00
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#define PLL_MASK_2 0xfbcfff00
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#define CLKSEL_DEFAULT 0x5a690000
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static int set_cpu_freq(unsigned int clk)
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{
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clk /= 1000000;
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/* Set clk to ext Xtal (LSN value 0) */
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writel(CLKSEL_DEFAULT, CLKSEL);
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switch (clk) {
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case 16:
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/* Bypass mode */
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return 0;
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case 50:
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writel(readl(PLLCON) & PLL_MASK_0, PLLCON);
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/* pll_off=1, M=25, N=1, OD=3, PLL_OUT_CLK=50M */
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writel((readl(PLLCON) & PLL_MASK_1) | 0x300191, PLLCON);
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/* pll_off=0, M=25, N=1, OD=3, PLL_OUT_CLK=50M */
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writel((readl(PLLCON) & PLL_MASK_2) | 0x300191, PLLCON);
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break;
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case 72:
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writel(readl(PLLCON) & PLL_MASK_0, PLLCON);
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/* pll_off=1, M=18, N=1, OD=2, PLL_OUT_CLK=72M */
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writel((readl(PLLCON) & PLL_MASK_1) | 0x200121, PLLCON);
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/* pll_off=0, M=18, N=1, OD=2, PLL_OUT_CLK=72M */
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writel((readl(PLLCON) & PLL_MASK_2) | 0x200121, PLLCON);
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break;
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case 100:
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writel(readl(PLLCON) & PLL_MASK_0, PLLCON);
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/* pll_off=1,M=25, N=1, OD=2, PLL_OUT_CLK=100M */
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writel((readl(PLLCON) & PLL_MASK_1) | 0x200191, PLLCON);
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/* pll_off=0,M=25, N=1, OD=2, PLL_OUT_CLK=100M */
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writel((readl(PLLCON) & PLL_MASK_2) | 0x200191, PLLCON);
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break;
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case 136:
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writel(readl(PLLCON) & PLL_MASK_0, PLLCON);
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/* pll_off=1, M=17, N=1, OD=1, PLL_OUT_CLK=136M */
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writel((readl(PLLCON) & PLL_MASK_1) | 0x100111, PLLCON);
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/* pll_off=0, M=17, N=1, OD=1, PLL_OUT_CLK=136M */
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writel((readl(PLLCON) & PLL_MASK_2) | 0x100111, PLLCON);
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break;
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case 144:
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writel(readl(PLLCON) & PLL_MASK_0, PLLCON);
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/* pll_off=1, M=18, N=1, OD=1, PLL_OUT_CLK=144M */
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writel((readl(PLLCON) & PLL_MASK_1) | 0x100121, PLLCON);
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/* pll_off=0, M=18, N=1, OD=1, PLL_OUT_CLK=144M */
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writel((readl(PLLCON) & PLL_MASK_2) | 0x100121, PLLCON);
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break;
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default:
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return -EINVAL;
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}
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while (!(readl(CLKSTAT) & 0x4))
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;
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/* Set clk from PLL on bus (LSN = 1) */
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writel(CLKSEL_DEFAULT | BIT(0), CLKSEL);
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return 0;
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}
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extern u8 __rom_end[];
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extern u8 __ram_start[];
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extern u8 __ram_end[];
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/*
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* Use mach_cpu_init() for .data section copy as board_early_init_f() will be
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* too late: initf_dm() will use a value of "av_" variable from not yet
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* initialized (by copy) area.
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*/
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int mach_cpu_init(void)
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{
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int offset;
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/* Don't relocate U-Boot */
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gd->flags |= GD_FLG_SKIP_RELOC;
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/* Copy data from ROM to RAM */
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u8 *src = __rom_end;
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u8 *dst = __ram_start;
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while (dst < __ram_end)
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*dst++ = *src++;
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/* Enable debug uart */
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#define DEBUG_UART_BASE 0x80014000
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#define DEBUG_UART_DLF_OFFSET 0xc0
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write_aux_reg(DEBUG_UART_BASE + DEBUG_UART_DLF_OFFSET, 1);
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offset = fdt_path_offset(gd->fdt_blob, "/cpu_card/core_clk");
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if (offset < 0)
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return offset;
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gd->cpu_clk = fdtdec_get_int(gd->fdt_blob, offset, "clock-frequency", 0);
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if (!gd->cpu_clk)
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return -EINVAL;
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/* If CPU freq > 100 MHz, divide eFLASH clock by 2 */
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if (gd->cpu_clk > 100000000) {
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u32 reg = readl(AHBCKDIV);
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reg &= ~(0xF << 8);
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reg |= 2 << 8;
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writel(reg, AHBCKDIV);
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}
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return set_cpu_freq(gd->cpu_clk);
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}
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#define IOTDK_RESET_SEQ 0x55AA6699
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void reset_cpu(ulong addr)
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{
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writel(IOTDK_RESET_SEQ, RESET_REG);
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}
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int checkboard(void)
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{
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puts("Board: Synopsys IoT Development Kit\n");
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return 0;
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};
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