249 lines
6.0 KiB
C
249 lines
6.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2008
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* Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
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*
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* Copyright 2004 Freescale Semiconductor.
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* (C) Copyright 2002,2003, Motorola Inc.
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* Xianghua Xiao, (X.Xiao@motorola.com)
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*
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* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
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*/
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#include <common.h>
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#include <env.h>
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#include <pci.h>
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#include <asm/processor.h>
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#include <asm/immap_85xx.h>
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#include <ioports.h>
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#include <flash.h>
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#include <linux/libfdt.h>
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#include <fdt_support.h>
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#include <asm/io.h>
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#include <i2c.h>
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#include <mb862xx.h>
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#include <video_fb.h>
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#include "upm_table.h"
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DECLARE_GLOBAL_DATA_PTR;
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extern flash_info_t flash_info[]; /* FLASH chips info */
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extern GraphicDevice mb862xx;
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void local_bus_init (void);
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ulong flash_get_size (ulong base, int banknum);
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int checkboard (void)
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{
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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char buf[64];
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int f;
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int i = env_get_f("serial#", buf, sizeof(buf));
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#ifdef CONFIG_PCI
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char *src;
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#endif
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puts("Board: Socrates");
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if (i > 0) {
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puts(", serial# ");
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puts(buf);
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}
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putc('\n');
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#if defined(CONFIG_PCI) || defined(CONFIG_DM_PCI)
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/* Check the PCI_clk sel bit */
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if (in_be32(&gur->porpllsr) & (1<<15)) {
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src = "SYSCLK";
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f = CONFIG_SYS_CLK_FREQ;
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} else {
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src = "PCI_CLK";
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f = CONFIG_PCI_CLK_FREQ;
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}
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printf ("PCI1: 32 bit, %d MHz (%s)\n", f/1000000, src);
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#else
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printf ("PCI1: disabled\n");
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#endif
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/*
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* Initialize local bus.
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*/
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local_bus_init ();
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return 0;
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}
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int misc_init_r (void)
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{
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/*
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* Adjust flash start and offset to detected values
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*/
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gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
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gd->bd->bi_flashoffset = 0;
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/*
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* Check if boot FLASH isn't max size
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*/
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if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH0)) {
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set_lbc_or(0, gd->bd->bi_flashstart |
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(CONFIG_SYS_OR0_PRELIM & 0x00007fff));
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set_lbc_br(0, gd->bd->bi_flashstart |
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(CONFIG_SYS_BR0_PRELIM & 0x00007fff));
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/*
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* Re-check to get correct base address
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*/
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flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1);
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}
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/*
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* Check if only one FLASH bank is available
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*/
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if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) {
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set_lbc_or(1, 0);
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set_lbc_br(1, 0);
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/*
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* Re-do flash protection upon new addresses
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*/
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flash_protect (FLAG_PROTECT_CLEAR,
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gd->bd->bi_flashstart, 0xffffffff,
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&flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
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/* Monitor protection ON by default */
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flash_protect (FLAG_PROTECT_SET,
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CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
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&flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
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/* Environment protection ON by default */
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flash_protect (FLAG_PROTECT_SET,
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CONFIG_ENV_ADDR,
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CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
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&flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
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/* Redundant environment protection ON by default */
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flash_protect (FLAG_PROTECT_SET,
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CONFIG_ENV_ADDR_REDUND,
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CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
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&flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
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}
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#if defined(CONFIG_DM_PCI)
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pci_init();
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#endif
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return 0;
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}
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/*
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* Initialize Local Bus
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*/
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void local_bus_init (void)
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{
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volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
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volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
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sys_info_t sysinfo;
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uint clkdiv;
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uint lbc_mhz;
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uint lcrr = CONFIG_SYS_LBC_LCRR;
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get_sys_info (&sysinfo);
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clkdiv = lbc->lcrr & LCRR_CLKDIV;
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lbc_mhz = sysinfo.freq_systembus / 1000000 / clkdiv;
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/* Disable PLL bypass for Local Bus Clock >= 66 MHz */
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if (lbc_mhz >= 66)
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lcrr &= ~LCRR_DBYP; /* DLL Enabled */
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else
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lcrr |= LCRR_DBYP; /* DLL Bypass */
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out_be32 (&lbc->lcrr, lcrr);
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asm ("sync;isync;msync");
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out_be32 (&lbc->ltesr, 0xffffffff); /* Clear LBC error interrupts */
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out_be32 (&lbc->lteir, 0xffffffff); /* Enable LBC error interrupts */
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out_be32 (&ecm->eedr, 0xffffffff); /* Clear ecm errors */
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out_be32 (&ecm->eeer, 0xffffffff); /* Enable ecm errors */
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/* Init UPMA for FPGA access */
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out_be32 (&lbc->mamr, 0x44440); /* Use a customer-supplied value */
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upmconfig (UPMA, (uint *)UPMTableA, sizeof(UPMTableA)/sizeof(int));
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/* Init UPMB for Lime controller access */
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out_be32 (&lbc->mbmr, 0x444440); /* Use a customer-supplied value */
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upmconfig (UPMB, (uint *)UPMTableB, sizeof(UPMTableB)/sizeof(int));
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}
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#ifdef CONFIG_BOARD_EARLY_INIT_R
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int board_early_init_r (void)
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{
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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/* set and reset the GPIO pin 2 which will reset the W83782G chip */
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out_8((unsigned char*)&gur->gpoutdr, 0x3F );
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out_be32((unsigned int*)&gur->gpiocr, 0x200 ); /* enable GPOut */
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udelay(200);
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out_8( (unsigned char*)&gur->gpoutdr, 0x1F );
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return (0);
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}
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#endif /* CONFIG_BOARD_EARLY_INIT_R */
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#ifdef CONFIG_OF_BOARD_SETUP
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int ft_board_setup(void *blob, bd_t *bd)
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{
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u32 val[12];
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int rc, i = 0;
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ft_cpu_setup(blob, bd);
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/* Fixup NOR FLASH mapping */
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val[i++] = 0; /* chip select number */
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val[i++] = 0; /* always 0 */
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val[i++] = gd->bd->bi_flashstart;
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val[i++] = gd->bd->bi_flashsize;
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#if defined(CONFIG_VIDEO_MB862xx)
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if (mb862xx.frameAdrs == CONFIG_SYS_LIME_BASE) {
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/* Fixup LIME mapping */
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val[i++] = 2; /* chip select number */
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val[i++] = 0; /* always 0 */
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val[i++] = CONFIG_SYS_LIME_BASE;
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val[i++] = CONFIG_SYS_LIME_SIZE;
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}
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#endif
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/* Fixup FPGA mapping */
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val[i++] = 3; /* chip select number */
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val[i++] = 0; /* always 0 */
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val[i++] = CONFIG_SYS_FPGA_BASE;
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val[i++] = CONFIG_SYS_FPGA_SIZE;
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rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
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val, i * sizeof(u32), 1);
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if (rc)
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printf("Unable to update localbus ranges, err=%s\n",
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fdt_strerror(rc));
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return 0;
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}
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#endif /* CONFIG_OF_BOARD_SETUP */
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#if defined(CONFIG_OF_SEPARATE)
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void *board_fdt_blob_setup(void)
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{
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void *fw_dtb;
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fw_dtb = (void *)(CONFIG_SYS_TEXT_BASE - CONFIG_ENV_SECT_SIZE);
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if (fdt_magic(fw_dtb) != FDT_MAGIC) {
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printf("DTB is not passed via %x\n", (u32)fw_dtb);
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return NULL;
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}
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return fw_dtb;
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}
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#endif
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int get_serial_clock(void)
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{
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return 333333330;
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}
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