287 lines
7.0 KiB
C
287 lines
7.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Board functions for Gumstix Pepper and AM335x-based boards
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*
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* Copyright (C) 2014, Gumstix, Incorporated - http://www.gumstix.com/
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* Based on board/ti/am335x/board.c from Texas Instruments, Inc.
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*/
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#include <common.h>
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#include <env.h>
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#include <errno.h>
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#include <serial.h>
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#include <spl.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/omap.h>
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#include <asm/arch/ddr_defs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/mem.h>
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#include <asm/io.h>
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#include <asm/emif.h>
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#include <asm/gpio.h>
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#include <i2c.h>
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#include <miiphy.h>
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#include <cpsw.h>
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#include <power/tps65217.h>
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#include <watchdog.h>
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#include "board.h"
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_SPL_BUILD
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#define OSC (V_OSCK/1000000)
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static const struct ddr_data ddr3_data = {
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.datardsratio0 = MT41K256M16HA125E_RD_DQS,
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.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
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.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
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.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
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};
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static const struct cmd_control ddr3_cmd_ctrl_data = {
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.cmd0csratio = MT41K256M16HA125E_RATIO,
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.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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.cmd1csratio = MT41K256M16HA125E_RATIO,
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.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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.cmd2csratio = MT41K256M16HA125E_RATIO,
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.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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};
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static struct emif_regs ddr3_emif_reg_data = {
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.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
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.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
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.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
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.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
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.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
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.zq_config = MT41K256M16HA125E_ZQ_CFG,
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.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
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};
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const struct dpll_params dpll_ddr3 = {400, OSC-1, 1, -1, -1, -1, -1};
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const struct ctrl_ioregs ioregs_ddr3 = {
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.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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};
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static const struct ddr_data ddr2_data = {
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.datardsratio0 = MT47H128M16RT25E_RD_DQS,
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.datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
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.datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
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};
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static const struct cmd_control ddr2_cmd_ctrl_data = {
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.cmd0csratio = MT47H128M16RT25E_RATIO,
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.cmd1csratio = MT47H128M16RT25E_RATIO,
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.cmd2csratio = MT47H128M16RT25E_RATIO,
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};
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static const struct emif_regs ddr2_emif_reg_data = {
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.sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
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.ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
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.sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
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.sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
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.sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
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.emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
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};
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const struct dpll_params dpll_ddr2 = {266, OSC-1, 1, -1, -1, -1, -1};
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const struct ctrl_ioregs ioregs_ddr2 = {
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.cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
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.cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
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.cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
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.dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
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.dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
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};
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static int read_eeprom(struct pepper_board_id *header)
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{
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if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
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return -ENODEV;
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}
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if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
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sizeof(struct pepper_board_id))) {
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return -EIO;
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}
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return 0;
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}
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const struct dpll_params *get_dpll_ddr_params(void)
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{
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struct pepper_board_id header;
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enable_i2c0_pin_mux();
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i2c_set_bus_num(0);
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if (read_eeprom(&header) < 0)
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return &dpll_ddr3;
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switch (header.device_vendor) {
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case GUMSTIX_PEPPER:
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return &dpll_ddr2;
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case GUMSTIX_PEPPER_DVI:
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return &dpll_ddr3;
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default:
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return &dpll_ddr3;
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}
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}
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void sdram_init(void)
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{
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const struct dpll_params *dpll = get_dpll_ddr_params();
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/*
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* Here we are assuming PLL clock reveals the type of RAM.
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* DDR2 = 266
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* DDR3 = 400
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* Note that DDR3 is the default.
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*/
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if (dpll->m == 266) {
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config_ddr(dpll->m, &ioregs_ddr2, &ddr2_data,
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&ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
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}
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else if (dpll->m == 400) {
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config_ddr(dpll->m, &ioregs_ddr3, &ddr3_data,
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&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
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}
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}
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#ifdef CONFIG_SPL_OS_BOOT
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int spl_start_uboot(void)
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{
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/* break into full u-boot on 'c' */
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return serial_tstc() && serial_getc() == 'c';
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}
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#endif
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void set_uart_mux_conf(void)
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{
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enable_uart0_pin_mux();
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}
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void set_mux_conf_regs(void)
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{
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enable_board_pin_mux();
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}
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#endif
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int board_init(void)
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{
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#if defined(CONFIG_HW_WATCHDOG)
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hw_watchdog_init();
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#endif
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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gpmc_init();
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return 0;
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}
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#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
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(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
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static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
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static void cpsw_control(int enabled)
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{
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/* VTP can be added here */
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return;
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}
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static struct cpsw_slave_data cpsw_slaves[] = {
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{
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.slave_reg_ofs = 0x208,
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.sliver_reg_ofs = 0xd80,
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.phy_addr = 0,
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.phy_if = PHY_INTERFACE_MODE_RGMII,
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},
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};
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static struct cpsw_platform_data cpsw_data = {
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.mdio_base = CPSW_MDIO_BASE,
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.cpsw_base = CPSW_BASE,
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.mdio_div = 0xff,
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.channels = 8,
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.cpdma_reg_ofs = 0x800,
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.slaves = 1,
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.slave_data = cpsw_slaves,
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.ale_reg_ofs = 0xd00,
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.ale_entries = 1024,
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.host_port_reg_ofs = 0x108,
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.hw_stats_reg_ofs = 0x900,
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.bd_ram_ofs = 0x2000,
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.mac_control = (1 << 5),
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.control = cpsw_control,
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.host_port_num = 0,
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.version = CPSW_CTRL_VERSION_2,
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};
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int board_eth_init(bd_t *bis)
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{
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int rv, n = 0;
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uint8_t mac_addr[6];
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uint32_t mac_hi, mac_lo;
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const char *devname;
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if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
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/* try reading mac address from efuse */
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mac_lo = readl(&cdev->macid0l);
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mac_hi = readl(&cdev->macid0h);
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mac_addr[0] = mac_hi & 0xFF;
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mac_addr[1] = (mac_hi & 0xFF00) >> 8;
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mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
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mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
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mac_addr[4] = mac_lo & 0xFF;
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mac_addr[5] = (mac_lo & 0xFF00) >> 8;
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if (is_valid_ethaddr(mac_addr))
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eth_env_set_enetaddr("ethaddr", mac_addr);
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}
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writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
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rv = cpsw_register(&cpsw_data);
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if (rv < 0)
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printf("Error %d registering CPSW switch\n", rv);
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else
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n += rv;
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/*
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*
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* CPSW RGMII Internal Delay Mode is not supported in all PVT
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* operating points. So we must set the TX clock delay feature
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* in the KSZ9021 PHY. Since we only support a single ethernet
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* device in U-Boot, we only do this for the current instance.
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*/
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devname = miiphy_get_current_dev();
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/* max rx/tx clock delay, min rx/tx control delay */
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miiphy_write(devname, 0x0, 0x0b, 0x8104);
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miiphy_write(devname, 0x0, 0xc, 0xa0a0);
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/* min rx data delay */
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miiphy_write(devname, 0x0, 0x0b, 0x8105);
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miiphy_write(devname, 0x0, 0x0c, 0x0000);
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/* min tx data delay */
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miiphy_write(devname, 0x0, 0x0b, 0x8106);
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miiphy_write(devname, 0x0, 0x0c, 0x0000);
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return n;
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}
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#endif
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