146 lines
3.8 KiB
C
146 lines
3.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
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* Copyright (C) 2017, Grinn - http://grinn-global.com/
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*/
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#include <common.h>
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#include <init.h>
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#include <asm/arch/chilisom.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/omap.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/mux.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/emif.h>
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#include <asm/io.h>
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#include <cpsw.h>
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#include <env.h>
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#include <errno.h>
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#include <miiphy.h>
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#include <spl.h>
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#include <watchdog.h>
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DECLARE_GLOBAL_DATA_PTR;
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static __maybe_unused struct ctrl_dev *cdev =
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(struct ctrl_dev *)CTRL_DEVICE_BASE;
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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static struct module_pin_mux uart0_pin_mux[] = {
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{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
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{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
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{-1},
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};
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static struct module_pin_mux mmc0_pin_mux[] = {
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{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
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{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
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{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
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{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
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{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
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{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
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{-1},
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};
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static struct module_pin_mux rmii1_pin_mux[] = {
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{OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS */
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{OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */
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{OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
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{OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TXD1 */
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{OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TXD0 */
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{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RXD1 */
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{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RXD0 */
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{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
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{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
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{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REFCLK */
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{-1},
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};
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static void enable_board_pin_mux(void)
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{
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chilisom_enable_pin_mux();
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/* chiliboard pinmux */
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configure_module_pin_mux(rmii1_pin_mux);
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configure_module_pin_mux(mmc0_pin_mux);
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}
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#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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void set_uart_mux_conf(void)
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{
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configure_module_pin_mux(uart0_pin_mux);
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}
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void set_mux_conf_regs(void)
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{
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enable_board_pin_mux();
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}
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void am33xx_spl_board_init(void)
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{
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chilisom_spl_board_init();
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}
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#endif
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/*
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* Basic board specific setup. Pinmux has been handled already.
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*/
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int board_init(void)
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{
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#if defined(CONFIG_HW_WATCHDOG)
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hw_watchdog_init();
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#endif
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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gpmc_init();
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return 0;
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}
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#ifdef CONFIG_BOARD_LATE_INIT
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int board_late_init(void)
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{
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#if !defined(CONFIG_SPL_BUILD)
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uint8_t mac_addr[6];
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uint32_t mac_hi, mac_lo;
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/* try reading mac address from efuse */
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mac_lo = readl(&cdev->macid0l);
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mac_hi = readl(&cdev->macid0h);
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mac_addr[0] = mac_hi & 0xFF;
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mac_addr[1] = (mac_hi & 0xFF00) >> 8;
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mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
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mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
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mac_addr[4] = mac_lo & 0xFF;
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mac_addr[5] = (mac_lo & 0xFF00) >> 8;
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if (!env_get("ethaddr")) {
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printf("<ethaddr> not set. Validating first E-fuse MAC\n");
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if (is_valid_ethaddr(mac_addr))
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eth_env_set_enetaddr("ethaddr", mac_addr);
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}
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mac_lo = readl(&cdev->macid1l);
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mac_hi = readl(&cdev->macid1h);
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mac_addr[0] = mac_hi & 0xFF;
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mac_addr[1] = (mac_hi & 0xFF00) >> 8;
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mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
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mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
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mac_addr[4] = mac_lo & 0xFF;
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mac_addr[5] = (mac_lo & 0xFF00) >> 8;
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if (!env_get("eth1addr")) {
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if (is_valid_ethaddr(mac_addr))
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eth_env_set_enetaddr("eth1addr", mac_addr);
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}
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#endif
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return 0;
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}
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#endif
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