183 lines
3.4 KiB
C
183 lines
3.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2013-2015, Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/siul.h>
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#include <asm/arch/lpddr2.h>
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#include <asm/arch/clock.h>
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#include <mmc.h>
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#include <fsl_esdhc_imx.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <i2c.h>
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DECLARE_GLOBAL_DATA_PTR;
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void setup_iomux_ddr(void)
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{
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lpddr2_config_iomux(DDR0);
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lpddr2_config_iomux(DDR1);
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}
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void ddr_phy_init(void)
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{
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}
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void ddr_ctrl_init(void)
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{
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config_mmdc(0);
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config_mmdc(1);
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}
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int dram_init(void)
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{
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setup_iomux_ddr();
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ddr_ctrl_init();
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gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
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return 0;
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}
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static void setup_iomux_uart(void)
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{
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/* Muxing for linflex */
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/* Replace the magic values after bringup */
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/* set TXD - MSCR[12] PA12 */
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writel(SIUL2_UART_TXD, SIUL2_MSCRn(SIUL2_UART0_TXD_PAD));
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/* set RXD - MSCR[11] - PA11 */
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writel(SIUL2_UART_MSCR_RXD, SIUL2_MSCRn(SIUL2_UART0_MSCR_RXD_PAD));
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/* set RXD - IMCR[200] - 200 */
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writel(SIUL2_UART_IMCR_RXD, SIUL2_IMCRn(SIUL2_UART0_IMCR_RXD_PAD));
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}
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static void setup_iomux_enet(void)
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{
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}
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static void setup_iomux_i2c(void)
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{
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}
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#ifdef CONFIG_SYS_USE_NAND
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void setup_iomux_nfc(void)
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{
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}
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#endif
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#ifdef CONFIG_FSL_ESDHC_IMX
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struct fsl_esdhc_cfg esdhc_cfg[1] = {
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{USDHC_BASE_ADDR},
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};
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int board_mmc_getcd(struct mmc *mmc)
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{
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/* eSDHC1 is always present */
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return 1;
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}
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int board_mmc_init(bd_t * bis)
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{
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esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_USDHC_CLK);
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/* Set iomux PADS for USDHC */
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/* PK6 pad: uSDHC clk */
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writel(SIUL2_USDHC_PAD_CTRL_CLK, SIUL2_MSCRn(150));
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writel(0x3, SIUL2_MSCRn(902));
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/* PK7 pad: uSDHC CMD */
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writel(SIUL2_USDHC_PAD_CTRL_CMD, SIUL2_MSCRn(151));
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writel(0x3, SIUL2_MSCRn(901));
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/* PK8 pad: uSDHC DAT0 */
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writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(152));
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writel(0x3, SIUL2_MSCRn(903));
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/* PK9 pad: uSDHC DAT1 */
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writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(153));
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writel(0x3, SIUL2_MSCRn(904));
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/* PK10 pad: uSDHC DAT2 */
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writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(154));
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writel(0x3, SIUL2_MSCRn(905));
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/* PK11 pad: uSDHC DAT3 */
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writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(155));
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writel(0x3, SIUL2_MSCRn(906));
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/* PK15 pad: uSDHC DAT4 */
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writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(159));
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writel(0x3, SIUL2_MSCRn(907));
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/* PL0 pad: uSDHC DAT5 */
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writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(160));
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writel(0x3, SIUL2_MSCRn(908));
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/* PL1 pad: uSDHC DAT6 */
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writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(161));
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writel(0x3, SIUL2_MSCRn(909));
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/* PL2 pad: uSDHC DAT7 */
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writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(162));
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writel(0x3, SIUL2_MSCRn(910));
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return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
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}
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#endif
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static void mscm_init(void)
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{
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struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_BASE_ADDR;
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int i;
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for (i = 0; i < MSCM_IRSPRC_NUM; i++)
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writew(MSCM_IRSPRC_CPn_EN, &mscmir->irsprc[i]);
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}
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int board_phy_config(struct phy_device *phydev)
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{
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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int board_early_init_f(void)
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{
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clock_init();
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mscm_init();
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setup_iomux_uart();
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setup_iomux_enet();
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setup_iomux_i2c();
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#ifdef CONFIG_SYS_USE_NAND
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setup_iomux_nfc();
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#endif
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return 0;
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}
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int board_init(void)
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{
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/* address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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return 0;
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}
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int checkboard(void)
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{
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puts("Board: s32v234evb\n");
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return 0;
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}
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