462 lines
12 KiB
INI
462 lines
12 KiB
INI
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2014 Freescale Semiconductor, Inc.
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* Jason Liu <r64343@freescale.com>
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*
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* Refer doc/README.imximage for more details about how-to configure
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* and create imximage boot image
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*
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* The syntax is taken as close as possible with the kwbimage
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*/
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/* image version */
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IMAGE_VERSION 2
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/*
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* Boot Device : one of
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* spi, sd (the board has no nand neither onenand)
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*/
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BOOT_FROM sd
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/*
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* Device Configuration Data (DCD)
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*
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* Each entry must have the format:
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* Addr-type Address Value
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*
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* where:
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* Addr-type register length (1,2 or 4 bytes)
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* Address absolute address of the register
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* value value to be stored in the register
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*/
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#ifdef CONFIG_MX6DL_LPDDR2
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/* IOMUX SETTINGS */
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 */
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DATA 4 0x020E04bc 0x00003028
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 */
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DATA 4 0x020E04c0 0x00003028
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 */
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DATA 4 0x020E04c4 0x00003028
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 */
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DATA 4 0x020E04c8 0x00003028
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4 */
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DATA 4 0x020E04cc 0x00003028
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5 */
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DATA 4 0x020E04d0 0x00003028
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6 */
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DATA 4 0x020E04d4 0x00003028
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7 */
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DATA 4 0x020E04d8 0x00003028
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */
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DATA 4 0x020E0470 0x00000038
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */
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DATA 4 0x020E0474 0x00000038
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 */
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DATA 4 0x020E0478 0x00000038
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 */
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DATA 4 0x020E047c 0x00000038
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 */
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DATA 4 0x020E0480 0x00000038
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 */
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DATA 4 0x020E0484 0x00000038
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 */
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DATA 4 0x020E0488 0x00000038
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 */
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DATA 4 0x020E048c 0x00000038
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */
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DATA 4 0x020E0464 0x00000038
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */
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DATA 4 0x020E0490 0x00000038
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 */
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DATA 4 0x020E04ac 0x00000038
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 */
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DATA 4 0x020E04b0 0x00000038
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */
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DATA 4 0x020E0494 0x00000038
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 */
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DATA 4 0x020E04a4 0x00000038
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 */
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DATA 4 0x020E04a8 0x00000038
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/*
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* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2
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* DSE can be configured using Group Control Register:
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* IOMUXC_SW_PAD_CTL_GRP_CTLDS
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*/
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DATA 4 0x020E04a0 0x00000000
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 */
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DATA 4 0x020E04b4 0x00000038
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 */
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DATA 4 0x020E04b8 0x00000038
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/* IOMUXC_SW_PAD_CTL_GRP_B0DS */
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DATA 4 0x020E0764 0x00000038
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/* IOMUXC_SW_PAD_CTL_GRP_B1DS */
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DATA 4 0x020E0770 0x00000038
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/* IOMUXC_SW_PAD_CTL_GRP_B2DS */
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DATA 4 0x020E0778 0x00000038
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/* IOMUXC_SW_PAD_CTL_GRP_B3DS */
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DATA 4 0x020E077c 0x00000038
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/* IOMUXC_SW_PAD_CTL_GRP_B4DS */
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DATA 4 0x020E0780 0x00000038
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/* IOMUXC_SW_PAD_CTL_GRP_B5DS */
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DATA 4 0x020E0784 0x00000038
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/* IOMUXC_SW_PAD_CTL_GRP_B6DS */
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DATA 4 0x020E078c 0x00000038
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/* IOMUXC_SW_PAD_CTL_GRP_B7DS */
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DATA 4 0x020E0748 0x00000038
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/* IOMUXC_SW_PAD_CTL_GRP_ADDDS */
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DATA 4 0x020E074c 0x00000038
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/* IOMUXC_SW_PAD_CTL_GRP_CTLDS */
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DATA 4 0x020E076c 0x00000038
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/* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */
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DATA 4 0x020E0750 0x00020000
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/* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */
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DATA 4 0x020E0754 0x00000000
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/* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */
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DATA 4 0x020E0760 0x00020000
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/* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */
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DATA 4 0x020E0774 0x00080000
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/*
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* DDR Controller Registers
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*
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* Manufacturer: Mocron
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* Device Part Number: MT42L64M64D2KH-18
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* Clock Freq.: 528MHz
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* MMDC channels: Both MMDC0, MMDC1
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*Density per CS in Gb: 256M
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* Chip Selects used: 2
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* Number of Banks: 8
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* Row address: 14
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* Column address: 9
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* Data bus width 32
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*/
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/* MMDC_P0_BASE_ADDR = 0x021b0000 */
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/* MMDC_P1_BASE_ADDR = 0x021b4000 */
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/* MMDC0_MDSCR, set the Configuration request bit during MMDC set up */
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DATA 4 0x021b001c 0x00008000
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/* MMDC0_MDSCR, set the Configuration request bit during MMDC set up */
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DATA 4 0x021b401c 0x00008000
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/*LPDDR2 ZQ params */
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DATA 4 0x021b085c 0x1b5f01ff
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DATA 4 0x021b485c 0x1b5f01ff
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/* Calibration setup. */
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/* DDR_PHY_P0_MPZQHWCTRL, enable on time ZQ calibration */
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DATA 4 0x021b0800 0xa1390003
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/*ca bus abs delay */
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DATA 4 0x021b0890 0x00400000
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/*ca bus abs delay */
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DATA 4 0x021b4890 0x00400000
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/* values of 20,40,50,60,7f tried. no difference seen */
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/* DDR_PHY_P1_MPWRCADL */
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DATA 4 0x021b48bc 0x00055555
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/*frc_msr.*/
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DATA 4 0x021b08b8 0x00000800
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/*frc_msr.*/
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DATA 4 0x021b48b8 0x00000800
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/* DDR_PHY_P0_MPREDQBY0DL3 */
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DATA 4 0x021b081c 0x33333333
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/* DDR_PHY_P0_MPREDQBY1DL3 */
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DATA 4 0x021b0820 0x33333333
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/* DDR_PHY_P0_MPREDQBY2DL3 */
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DATA 4 0x021b0824 0x33333333
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/* DDR_PHY_P0_MPREDQBY3DL3 */
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DATA 4 0x021b0828 0x33333333
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/* DDR_PHY_P1_MPREDQBY0DL3 */
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DATA 4 0x021b481c 0x33333333
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/* DDR_PHY_P1_MPREDQBY1DL3 */
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DATA 4 0x021b4820 0x33333333
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/* DDR_PHY_P1_MPREDQBY2DL3 */
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DATA 4 0x021b4824 0x33333333
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/* DDR_PHY_P1_MPREDQBY3DL3 */
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DATA 4 0x021b4828 0x33333333
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/*
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* Read and write data delay, per byte.
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* For optimized DDR operation it is recommended to run mmdc_calibration
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* on your board, and replace 4 delay register assigns with resulted values
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* Note:
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* a. DQS gating is not relevant for LPDDR2. DSQ gating calibration section
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* should be skipped, or the write/read calibration comming after that
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* will stall
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* b. The calibration code that runs for both MMDC0 & MMDC1 should be used.
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*/
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DATA 4 0x021b0848 0x4b4b524f
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DATA 4 0x021b4848 0x494f4c44
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DATA 4 0x021b0850 0x3c3d303c
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DATA 4 0x021b4850 0x3c343d38
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/*dqs gating dis */
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DATA 4 0x021b083c 0x20000000
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DATA 4 0x021b0840 0x0
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DATA 4 0x021b483c 0x20000000
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DATA 4 0x021b4840 0x0
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/*clk delay */
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DATA 4 0x021b0858 0xa00
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/*clk delay */
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DATA 4 0x021b4858 0xa00
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/*frc_msr */
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DATA 4 0x021b08b8 0x00000800
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/*frc_msr */
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DATA 4 0x021b48b8 0x00000800
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/* Calibration setup end */
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/* Channel0 - startng address 0x80000000 */
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/* MMDC0_MDCFG0 */
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DATA 4 0x021b000c 0x34386145
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/* MMDC0_MDPDC */
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DATA 4 0x021b0004 0x00020036
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/* MMDC0_MDCFG1 */
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DATA 4 0x021b0010 0x00100c83
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/* MMDC0_MDCFG2 */
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DATA 4 0x021b0014 0x000000Dc
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/* MMDC0_MDMISC */
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DATA 4 0x021b0018 0x0000174C
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/* MMDC0_MDRWD;*/
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DATA 4 0x021b002c 0x0f9f26d2
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/* MMDC0_MDOR */
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DATA 4 0x021b0030 0x009f0e10
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/* MMDC0_MDCFG3LP */
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DATA 4 0x021b0038 0x00190778
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/* MMDC0_MDOTC */
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DATA 4 0x021b0008 0x00000000
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/* CS0_END */
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DATA 4 0x021b0040 0x0000005f
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/* ROC */
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DATA 4 0x021b0404 0x0000000f
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/* MMDC0_MDCTL */
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DATA 4 0x021b0000 0xc3010000
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/* Channel1 - starting address 0x10000000 */
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/* MMDC1_MDCFG0 */
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DATA 4 0x021b400c 0x34386145
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/* MMDC1_MDPDC */
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DATA 4 0x021b4004 0x00020036
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/* MMDC1_MDCFG1 */
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DATA 4 0x021b4010 0x00100c83
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/* MMDC1_MDCFG2 */
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DATA 4 0x021b4014 0x000000Dc
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/* MMDC1_MDMISC */
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DATA 4 0x021b4018 0x0000174C
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/* MMDC1_MDRWD;*/
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DATA 4 0x021b402c 0x0f9f26d2
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/* MMDC1_MDOR */
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DATA 4 0x021b4030 0x009f0e10
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/* MMDC1_MDCFG3LP */
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DATA 4 0x021b4038 0x00190778
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/* MMDC1_MDOTC */
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DATA 4 0x021b4008 0x00000000
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/* CS0_END */
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DATA 4 0x021b4040 0x0000003f
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/* MMDC1_MDCTL */
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DATA 4 0x021b4000 0xc3010000
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/* Channel0 : Configure DDR device:*/
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/* MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 */
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DATA 4 0x021b001c 0x003f8030
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/* MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff */
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DATA 4 0x021b001c 0xff0a8030
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/* MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=a2 */
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DATA 4 0x021b001c 0xa2018030
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/* MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=6. tcl=8, tcwl=4 */
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DATA 4 0x021b001c 0x06028030
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/* MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=2.drive=240/6 */
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DATA 4 0x021b001c 0x01038030
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/* Channel1 : Configure DDR device:*/
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/* MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 */
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DATA 4 0x021b401c 0x003f8030
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/* MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff */
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DATA 4 0x021b401c 0xff0a8030
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/* MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=a2 */
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DATA 4 0x021b401c 0xa2018030
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/* MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=6. tcl=8, tcwl=4 */
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DATA 4 0x021b401c 0x06028030
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/* MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=2.drive=240/6 */
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DATA 4 0x021b401c 0x01038030
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/* MMDC0_MDREF */
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DATA 4 0x021b0020 0x00005800
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/* MMDC1_MDREF */
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DATA 4 0x021b4020 0x00005800
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/* DDR_PHY_P0_MPODTCTRL */
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DATA 4 0x021b0818 0x0
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/* DDR_PHY_P1_MPODTCTRL */
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DATA 4 0x021b4818 0x0
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/*
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* calibration values based on calibration compare of 0x00ffff00:
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* Note, these calibration values are based on Freescale's board
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* May need to run calibration on target board to fine tune these
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*/
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/* DDR_PHY_P0_MPZQHWCTRL, enable automatic ZQ calibration */
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DATA 4 0x021b0800 0xa1310003
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/* DDR_PHY_P0_MPMUR0, frc_msr */
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DATA 4 0x021b08b8 0x00000800
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/* DDR_PHY_P1_MPMUR0, frc_msr */
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DATA 4 0x021b48b8 0x00000800
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/*
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* MMDC0_MDSCR, clear this register
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* (especially the configuration bit as initialization is complete)
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*/
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DATA 4 0x021b001c 0x00000000
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/*
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* MMDC0_MDSCR, clear this register
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* (especially the configuration bit as initialization is complete)
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*/
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DATA 4 0x021b401c 0x00000000
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DATA 4 0x020c4068 0x00C03F3F
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DATA 4 0x020c406c 0x0030FC03
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DATA 4 0x020c4070 0x0FFFC000
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DATA 4 0x020c4074 0x3FF00000
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DATA 4 0x020c4078 0x00FFF300
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DATA 4 0x020c407c 0x0F0000C3
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DATA 4 0x020c4080 0x000003FF
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DATA 4 0x020e0010 0xF00000CF
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DATA 4 0x020e0018 0x007F007F
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DATA 4 0x020e001c 0x007F007F
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#else /* CONFIG_MX6DL_LPDDR2 */
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DATA 4 0x020e0798 0x000c0000
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DATA 4 0x020e0758 0x00000000
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DATA 4 0x020e0588 0x00000030
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DATA 4 0x020e0594 0x00000030
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DATA 4 0x020e056c 0x00000030
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DATA 4 0x020e0578 0x00000030
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DATA 4 0x020e074c 0x00000030
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DATA 4 0x020e057c 0x00000030
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DATA 4 0x020e0590 0x00003000
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DATA 4 0x020e0598 0x00003000
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DATA 4 0x020e058c 0x00000000
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DATA 4 0x020e059c 0x00003030
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DATA 4 0x020e05a0 0x00003030
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DATA 4 0x020e078c 0x00000030
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DATA 4 0x020e0750 0x00020000
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DATA 4 0x020e05a8 0x00000030
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DATA 4 0x020e05b0 0x00000030
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DATA 4 0x020e0524 0x00000030
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DATA 4 0x020e051c 0x00000030
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DATA 4 0x020e0518 0x00000030
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DATA 4 0x020e050c 0x00000030
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DATA 4 0x020e05b8 0x00000030
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DATA 4 0x020e05c0 0x00000030
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DATA 4 0x020e0774 0x00020000
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DATA 4 0x020e0784 0x00000030
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DATA 4 0x020e0788 0x00000030
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DATA 4 0x020e0794 0x00000030
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DATA 4 0x020e079c 0x00000030
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DATA 4 0x020e07a0 0x00000030
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DATA 4 0x020e07a4 0x00000030
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DATA 4 0x020e07a8 0x00000030
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DATA 4 0x020e0748 0x00000030
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DATA 4 0x020e05ac 0x00000030
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DATA 4 0x020e05b4 0x00000030
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DATA 4 0x020e0528 0x00000030
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DATA 4 0x020e0520 0x00000030
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DATA 4 0x020e0514 0x00000030
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DATA 4 0x020e0510 0x00000030
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DATA 4 0x020e05bc 0x00000030
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DATA 4 0x020e05c4 0x00000030
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DATA 4 0x021b0800 0xa1390003
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DATA 4 0x021b4800 0xa1390003
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DATA 4 0x021b080c 0x001F001F
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DATA 4 0x021b0810 0x001F001F
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DATA 4 0x021b480c 0x00370037
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DATA 4 0x021b4810 0x00370037
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DATA 4 0x021b083c 0x422f0220
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DATA 4 0x021b0840 0x021f0219
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DATA 4 0x021b483C 0x422f0220
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DATA 4 0x021b4840 0x022d022f
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DATA 4 0x021b0848 0x47494b49
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DATA 4 0x021b4848 0x48484c47
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DATA 4 0x021b0850 0x39382b2f
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DATA 4 0x021b4850 0x2f35312c
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DATA 4 0x021b081c 0x33333333
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DATA 4 0x021b0820 0x33333333
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DATA 4 0x021b0824 0x33333333
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DATA 4 0x021b0828 0x33333333
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DATA 4 0x021b481c 0x33333333
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DATA 4 0x021b4820 0x33333333
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DATA 4 0x021b4824 0x33333333
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DATA 4 0x021b4828 0x33333333
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DATA 4 0x021b08b8 0x00000800
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DATA 4 0x021b48b8 0x00000800
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DATA 4 0x021b0004 0x0002002d
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DATA 4 0x021b0008 0x00333030
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DATA 4 0x021b000c 0x40445323
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DATA 4 0x021b0010 0xb66e8c63
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DATA 4 0x021b0014 0x01ff00db
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DATA 4 0x021b0018 0x00081740
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DATA 4 0x021b001c 0x00008000
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DATA 4 0x021b002c 0x000026d2
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DATA 4 0x021b0030 0x00440e21
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#ifdef CONFIG_DDR_32BIT
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DATA 4 0x021b0040 0x00000017
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DATA 4 0x021b0000 0xc3190000
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#else
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DATA 4 0x021b0040 0x00000027
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DATA 4 0x021b0000 0xc31a0000
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#endif
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DATA 4 0x021b001c 0x04008032
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DATA 4 0x021b001c 0x0400803a
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DATA 4 0x021b001c 0x00008033
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DATA 4 0x021b001c 0x0000803b
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DATA 4 0x021b001c 0x00428031
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DATA 4 0x021b001c 0x00428039
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DATA 4 0x021b001c 0x07208030
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DATA 4 0x021b001c 0x07208038
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DATA 4 0x021b001c 0x04008040
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DATA 4 0x021b001c 0x04008048
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DATA 4 0x021b0020 0x00005800
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DATA 4 0x021b0818 0x00000007
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DATA 4 0x021b4818 0x00000007
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DATA 4 0x021b0004 0x0002556d
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DATA 4 0x021b4004 0x00011006
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DATA 4 0x021b001c 0x00000000
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DATA 4 0x020c4068 0x00C03F3F
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DATA 4 0x020c406c 0x0030FC03
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DATA 4 0x020c4070 0x0FFFC000
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DATA 4 0x020c4074 0x3FF00000
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DATA 4 0x020c4078 0x00FFF300
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DATA 4 0x020c407c 0x0F0000C3
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DATA 4 0x020c4080 0x000003FF
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DATA 4 0x020e0010 0xF00000CF
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DATA 4 0x020e0018 0x007F007F
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DATA 4 0x020e001c 0x007F007F
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#endif /* CONFIG_MX6DL_LPDDR2 */
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