1018 lines
20 KiB
C
1018 lines
20 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2017-2018 NXP
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*/
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#include <common.h>
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#include <env.h>
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#include <i2c.h>
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#include <malloc.h>
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#include <errno.h>
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#include <netdev.h>
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#include <fsl_ifc.h>
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#include <fsl_ddr.h>
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#include <fsl_sec.h>
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#include <asm/io.h>
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#include <fdt_support.h>
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#include <linux/libfdt.h>
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#include <fsl-mc/fsl_mc.h>
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#include <env_internal.h>
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#include <asm/arch-fsl-layerscape/soc.h>
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#include <asm/arch/ppa.h>
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#include <hwconfig.h>
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#include <asm/arch/fsl_serdes.h>
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#include <asm/arch/soc.h>
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#include <asm/arch-fsl-layerscape/fsl_icid.h>
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#include "../common/qixis.h"
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#include "ls1088a_qixis.h"
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#include "../common/vid.h"
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#include <fsl_immap.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_TARGET_LS1088AQDS
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#ifdef CONFIG_TFABOOT
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struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
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{
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"nor0",
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CONFIG_SYS_NOR0_CSPR_EARLY,
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CONFIG_SYS_NOR0_CSPR_EXT,
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CONFIG_SYS_NOR_AMASK,
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CONFIG_SYS_NOR_CSOR,
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{
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CONFIG_SYS_NOR_FTIM0,
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CONFIG_SYS_NOR_FTIM1,
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CONFIG_SYS_NOR_FTIM2,
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CONFIG_SYS_NOR_FTIM3
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},
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0,
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CONFIG_SYS_NOR0_CSPR,
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0,
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},
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{
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"nor1",
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CONFIG_SYS_NOR1_CSPR_EARLY,
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CONFIG_SYS_NOR0_CSPR_EXT,
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CONFIG_SYS_NOR_AMASK_EARLY,
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CONFIG_SYS_NOR_CSOR,
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{
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CONFIG_SYS_NOR_FTIM0,
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CONFIG_SYS_NOR_FTIM1,
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CONFIG_SYS_NOR_FTIM2,
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CONFIG_SYS_NOR_FTIM3
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},
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0,
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CONFIG_SYS_NOR1_CSPR,
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CONFIG_SYS_NOR_AMASK,
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},
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{
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"nand",
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CONFIG_SYS_NAND_CSPR,
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CONFIG_SYS_NAND_CSPR_EXT,
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CONFIG_SYS_NAND_AMASK,
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CONFIG_SYS_NAND_CSOR,
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{
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CONFIG_SYS_NAND_FTIM0,
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CONFIG_SYS_NAND_FTIM1,
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CONFIG_SYS_NAND_FTIM2,
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CONFIG_SYS_NAND_FTIM3
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},
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},
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{
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"fpga",
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CONFIG_SYS_FPGA_CSPR,
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CONFIG_SYS_FPGA_CSPR_EXT,
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SYS_FPGA_AMASK,
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CONFIG_SYS_FPGA_CSOR,
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{
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SYS_FPGA_CS_FTIM0,
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SYS_FPGA_CS_FTIM1,
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SYS_FPGA_CS_FTIM2,
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SYS_FPGA_CS_FTIM3
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},
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0,
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SYS_FPGA_CSPR_FINAL,
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0,
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}
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};
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struct ifc_regs ifc_cfg_qspi_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
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{
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"nand",
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CONFIG_SYS_NAND_CSPR,
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CONFIG_SYS_NAND_CSPR_EXT,
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CONFIG_SYS_NAND_AMASK,
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CONFIG_SYS_NAND_CSOR,
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{
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CONFIG_SYS_NAND_FTIM0,
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CONFIG_SYS_NAND_FTIM1,
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CONFIG_SYS_NAND_FTIM2,
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CONFIG_SYS_NAND_FTIM3
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},
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},
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{
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"reserved",
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},
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{
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"fpga",
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CONFIG_SYS_FPGA_CSPR,
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CONFIG_SYS_FPGA_CSPR_EXT,
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SYS_FPGA_AMASK,
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CONFIG_SYS_FPGA_CSOR,
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{
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SYS_FPGA_CS_FTIM0,
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SYS_FPGA_CS_FTIM1,
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SYS_FPGA_CS_FTIM2,
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SYS_FPGA_CS_FTIM3
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},
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0,
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SYS_FPGA_CSPR_FINAL,
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0,
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}
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};
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void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
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{
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enum boot_src src = get_boot_src();
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if (src == BOOT_SOURCE_QSPI_NOR)
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regs_info->regs = ifc_cfg_qspi_nor_boot;
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else
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regs_info->regs = ifc_cfg_ifc_nor_boot;
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regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
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}
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#endif /* CONFIG_TFABOOT */
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#endif /* CONFIG_TARGET_LS1088AQDS */
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int board_early_init_f(void)
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{
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#if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_TARGET_LS1088AQDS)
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i2c_early_init_f();
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#endif
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fsl_lsch3_early_init_f();
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return 0;
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}
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#ifdef CONFIG_FSL_QIXIS
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unsigned long long get_qixis_addr(void)
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{
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unsigned long long addr;
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if (gd->flags & GD_FLG_RELOC)
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addr = QIXIS_BASE_PHYS;
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else
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addr = QIXIS_BASE_PHYS_EARLY;
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/*
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* IFC address under 256MB is mapped to 0x30000000, any address above
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* is mapped to 0x5_10000000 up to 4GB.
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*/
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addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
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return addr;
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}
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#endif
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#if defined(CONFIG_VID)
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int init_func_vid(void)
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{
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if (adjust_vdd(0) < 0)
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printf("core voltage not adjusted\n");
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return 0;
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}
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#endif
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int is_pb_board(void)
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{
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u8 board_id;
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board_id = QIXIS_READ(id);
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if (board_id == LS1088ARDB_PB_BOARD)
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return 1;
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else
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return 0;
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}
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int fixup_ls1088ardb_pb_banner(void *fdt)
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{
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fdt_setprop_string(fdt, 0, "model", "LS1088ARDB-PB Board");
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return 0;
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}
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#if !defined(CONFIG_SPL_BUILD)
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int checkboard(void)
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{
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#ifdef CONFIG_TFABOOT
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enum boot_src src = get_boot_src();
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#endif
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char buf[64];
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u8 sw;
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static const char *const freq[] = {"100", "125", "156.25",
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"100 separate SSCG"};
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int clock;
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#ifdef CONFIG_TARGET_LS1088AQDS
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printf("Board: LS1088A-QDS, ");
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#else
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if (is_pb_board())
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printf("Board: LS1088ARDB-PB, ");
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else
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printf("Board: LS1088A-RDB, ");
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#endif
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sw = QIXIS_READ(arch);
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printf("Board Arch: V%d, ", sw >> 4);
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#ifdef CONFIG_TARGET_LS1088AQDS
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printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
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#else
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printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
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#endif
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memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
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sw = QIXIS_READ(brdcfg[0]);
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sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
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#ifdef CONFIG_TFABOOT
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if (src == BOOT_SOURCE_SD_MMC)
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puts("SD card\n");
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#else
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#ifdef CONFIG_SD_BOOT
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puts("SD card\n");
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#endif
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#endif /* CONFIG_TFABOOT */
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switch (sw) {
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#ifdef CONFIG_TARGET_LS1088AQDS
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case 0:
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case 1:
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case 2:
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case 3:
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case 4:
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case 5:
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case 6:
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case 7:
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printf("vBank: %d\n", sw);
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break;
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case 8:
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puts("PromJet\n");
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break;
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case 15:
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puts("IFCCard\n");
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break;
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case 14:
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#else
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case 0:
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#endif
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puts("QSPI:");
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sw = QIXIS_READ(brdcfg[0]);
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sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
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if (sw == 0 || sw == 4)
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puts("0\n");
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else if (sw == 1)
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puts("1\n");
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else
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puts("EMU\n");
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break;
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default:
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printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
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break;
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}
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#ifdef CONFIG_TARGET_LS1088AQDS
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printf("FPGA: v%d (%s), build %d",
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(int)QIXIS_READ(scver), qixis_read_tag(buf),
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(int)qixis_read_minor());
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/* the timestamp string contains "\n" at the end */
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printf(" on %s", qixis_read_time(buf));
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#else
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printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
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#endif
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/*
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* Display the actual SERDES reference clocks as configured by the
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* dip switches on the board. Note that the SWx registers could
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* technically be set to force the reference clocks to match the
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* values that the SERDES expects (or vice versa). For now, however,
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* we just display both values and hope the user notices when they
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* don't match.
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*/
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puts("SERDES1 Reference : ");
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sw = QIXIS_READ(brdcfg[2]);
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clock = (sw >> 6) & 3;
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printf("Clock1 = %sMHz ", freq[clock]);
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clock = (sw >> 4) & 3;
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printf("Clock2 = %sMHz", freq[clock]);
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puts("\nSERDES2 Reference : ");
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clock = (sw >> 2) & 3;
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printf("Clock1 = %sMHz ", freq[clock]);
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clock = (sw >> 0) & 3;
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printf("Clock2 = %sMHz\n", freq[clock]);
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return 0;
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}
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#endif
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bool if_board_diff_clk(void)
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{
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#ifdef CONFIG_TARGET_LS1088AQDS
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u8 diff_conf = QIXIS_READ(brdcfg[11]);
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return diff_conf & 0x40;
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#else
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u8 diff_conf = QIXIS_READ(dutcfg[11]);
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return diff_conf & 0x80;
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#endif
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}
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unsigned long get_board_sys_clk(void)
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{
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u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
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switch (sysclk_conf & 0x0f) {
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case QIXIS_SYSCLK_83:
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return 83333333;
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case QIXIS_SYSCLK_100:
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return 100000000;
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case QIXIS_SYSCLK_125:
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return 125000000;
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case QIXIS_SYSCLK_133:
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return 133333333;
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case QIXIS_SYSCLK_150:
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return 150000000;
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case QIXIS_SYSCLK_160:
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return 160000000;
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case QIXIS_SYSCLK_166:
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return 166666666;
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}
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return 66666666;
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}
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unsigned long get_board_ddr_clk(void)
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{
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u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
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if (if_board_diff_clk())
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return get_board_sys_clk();
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switch ((ddrclk_conf & 0x30) >> 4) {
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case QIXIS_DDRCLK_100:
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return 100000000;
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case QIXIS_DDRCLK_125:
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return 125000000;
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case QIXIS_DDRCLK_133:
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return 133333333;
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}
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return 66666666;
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}
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int select_i2c_ch_pca9547(u8 ch)
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{
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int ret;
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#ifndef CONFIG_DM_I2C
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ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
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#else
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struct udevice *dev;
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ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
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if (!ret)
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ret = dm_i2c_write(dev, 0, &ch, 1);
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#endif
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if (ret) {
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puts("PCA: failed to select proper channel\n");
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return ret;
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}
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return 0;
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}
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#if !defined(CONFIG_SPL_BUILD)
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void board_retimer_init(void)
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{
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u8 reg;
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/* Retimer is connected to I2C1_CH5 */
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select_i2c_ch_pca9547(I2C_MUX_CH5);
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/* Access to Control/Shared register */
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reg = 0x0;
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#ifndef CONFIG_DM_I2C
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i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
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#else
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struct udevice *dev;
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i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR, 1, &dev);
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dm_i2c_write(dev, 0xff, ®, 1);
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#endif
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/* Read device revision and ID */
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#ifndef CONFIG_DM_I2C
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i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1);
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#else
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dm_i2c_read(dev, 1, ®, 1);
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#endif
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debug("Retimer version id = 0x%x\n", reg);
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/* Enable Broadcast. All writes target all channel register sets */
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reg = 0x0c;
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#ifndef CONFIG_DM_I2C
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i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
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#else
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dm_i2c_write(dev, 0xff, ®, 1);
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#endif
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/* Reset Channel Registers */
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#ifndef CONFIG_DM_I2C
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i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1);
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#else
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dm_i2c_read(dev, 0, ®, 1);
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#endif
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reg |= 0x4;
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#ifndef CONFIG_DM_I2C
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i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1);
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#else
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dm_i2c_write(dev, 0, ®, 1);
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#endif
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/* Set data rate as 10.3125 Gbps */
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reg = 0x90;
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#ifndef CONFIG_DM_I2C
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i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1);
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#else
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dm_i2c_write(dev, 0x60, ®, 1);
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#endif
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reg = 0xb3;
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#ifndef CONFIG_DM_I2C
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i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1);
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#else
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dm_i2c_write(dev, 0x61, ®, 1);
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#endif
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reg = 0x90;
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#ifndef CONFIG_DM_I2C
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i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1);
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#else
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dm_i2c_write(dev, 0x62, ®, 1);
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#endif
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reg = 0xb3;
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#ifndef CONFIG_DM_I2C
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i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1);
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#else
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dm_i2c_write(dev, 0x63, ®, 1);
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#endif
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reg = 0xcd;
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#ifndef CONFIG_DM_I2C
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i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1);
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#else
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dm_i2c_write(dev, 0x64, ®, 1);
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#endif
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/* Select VCO Divider to full rate (000) */
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#ifndef CONFIG_DM_I2C
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i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1);
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#else
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dm_i2c_read(dev, 0x2F, ®, 1);
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#endif
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reg &= 0x0f;
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reg |= 0x70;
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#ifndef CONFIG_DM_I2C
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i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1);
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#else
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dm_i2c_write(dev, 0x2F, ®, 1);
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#endif
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#ifdef CONFIG_TARGET_LS1088AQDS
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/* Retimer is connected to I2C1_CH5 */
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select_i2c_ch_pca9547(I2C_MUX_CH5);
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/* Access to Control/Shared register */
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reg = 0x0;
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#ifndef CONFIG_DM_I2C
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i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1);
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#else
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i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR2, 1, &dev);
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dm_i2c_write(dev, 0xff, ®, 1);
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#endif
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/* Read device revision and ID */
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#ifndef CONFIG_DM_I2C
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i2c_read(I2C_RETIMER_ADDR2, 1, 1, ®, 1);
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#else
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dm_i2c_read(dev, 1, ®, 1);
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#endif
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debug("Retimer version id = 0x%x\n", reg);
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/* Enable Broadcast. All writes target all channel register sets */
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reg = 0x0c;
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#ifndef CONFIG_DM_I2C
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i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1);
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#else
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dm_i2c_write(dev, 0xff, ®, 1);
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#endif
|
|
|
|
/* Reset Channel Registers */
|
|
#ifndef CONFIG_DM_I2C
|
|
i2c_read(I2C_RETIMER_ADDR2, 0, 1, ®, 1);
|
|
#else
|
|
dm_i2c_read(dev, 0, ®, 1);
|
|
#endif
|
|
reg |= 0x4;
|
|
#ifndef CONFIG_DM_I2C
|
|
i2c_write(I2C_RETIMER_ADDR2, 0, 1, ®, 1);
|
|
#else
|
|
dm_i2c_write(dev, 0, ®, 1);
|
|
#endif
|
|
|
|
/* Set data rate as 10.3125 Gbps */
|
|
reg = 0x90;
|
|
#ifndef CONFIG_DM_I2C
|
|
i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, ®, 1);
|
|
#else
|
|
dm_i2c_write(dev, 0x60, ®, 1);
|
|
#endif
|
|
reg = 0xb3;
|
|
#ifndef CONFIG_DM_I2C
|
|
i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, ®, 1);
|
|
#else
|
|
dm_i2c_write(dev, 0x61, ®, 1);
|
|
#endif
|
|
reg = 0x90;
|
|
#ifndef CONFIG_DM_I2C
|
|
i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, ®, 1);
|
|
#else
|
|
dm_i2c_write(dev, 0x62, ®, 1);
|
|
#endif
|
|
reg = 0xb3;
|
|
#ifndef CONFIG_DM_I2C
|
|
i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, ®, 1);
|
|
#else
|
|
dm_i2c_write(dev, 0x63, ®, 1);
|
|
#endif
|
|
reg = 0xcd;
|
|
#ifndef CONFIG_DM_I2C
|
|
i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, ®, 1);
|
|
#else
|
|
dm_i2c_write(dev, 0x64, ®, 1);
|
|
#endif
|
|
|
|
/* Select VCO Divider to full rate (000) */
|
|
#ifndef CONFIG_DM_I2C
|
|
i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1);
|
|
#else
|
|
dm_i2c_read(dev, 0x2F, ®, 1);
|
|
#endif
|
|
reg &= 0x0f;
|
|
reg |= 0x70;
|
|
#ifndef CONFIG_DM_I2C
|
|
i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1);
|
|
#else
|
|
dm_i2c_write(dev, 0x2F, ®, 1);
|
|
#endif
|
|
|
|
#endif
|
|
/*return the default channel*/
|
|
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
|
|
}
|
|
|
|
#ifdef CONFIG_MISC_INIT_R
|
|
int misc_init_r(void)
|
|
{
|
|
#ifdef CONFIG_TARGET_LS1088ARDB
|
|
u8 brdcfg5;
|
|
|
|
if (hwconfig("esdhc-force-sd")) {
|
|
brdcfg5 = QIXIS_READ(brdcfg[5]);
|
|
brdcfg5 &= ~BRDCFG5_SPISDHC_MASK;
|
|
brdcfg5 |= BRDCFG5_FORCE_SD;
|
|
QIXIS_WRITE(brdcfg[5], brdcfg5);
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_TARGET_LS1088AQDS
|
|
u8 brdcfg4, brdcfg5;
|
|
|
|
if (hwconfig("dspi-on-board")) {
|
|
brdcfg4 = QIXIS_READ(brdcfg[4]);
|
|
brdcfg4 &= ~BRDCFG4_USBOSC_MASK;
|
|
brdcfg4 |= BRDCFG4_SPI;
|
|
QIXIS_WRITE(brdcfg[4], brdcfg4);
|
|
|
|
brdcfg5 = QIXIS_READ(brdcfg[5]);
|
|
brdcfg5 &= ~BRDCFG5_SPR_MASK;
|
|
brdcfg5 |= BRDCFG5_SPI_ON_BOARD;
|
|
QIXIS_WRITE(brdcfg[5], brdcfg5);
|
|
} else if (hwconfig("dspi-off-board")) {
|
|
brdcfg4 = QIXIS_READ(brdcfg[4]);
|
|
brdcfg4 &= ~BRDCFG4_USBOSC_MASK;
|
|
brdcfg4 |= BRDCFG4_SPI;
|
|
QIXIS_WRITE(brdcfg[4], brdcfg4);
|
|
|
|
brdcfg5 = QIXIS_READ(brdcfg[5]);
|
|
brdcfg5 &= ~BRDCFG5_SPR_MASK;
|
|
brdcfg5 |= BRDCFG5_SPI_OFF_BOARD;
|
|
QIXIS_WRITE(brdcfg[5], brdcfg5);
|
|
}
|
|
#endif
|
|
return 0;
|
|
}
|
|
#endif
|
|
#endif
|
|
|
|
int i2c_multiplexer_select_vid_channel(u8 channel)
|
|
{
|
|
return select_i2c_ch_pca9547(channel);
|
|
}
|
|
|
|
#ifdef CONFIG_TARGET_LS1088AQDS
|
|
/* read the current value(SVDD) of the LTM Regulator Voltage */
|
|
int get_serdes_volt(void)
|
|
{
|
|
int ret, vcode = 0;
|
|
u8 chan = PWM_CHANNEL0;
|
|
|
|
/* Select the PAGE 0 using PMBus commands PAGE for VDD */
|
|
#ifndef CONFIG_DM_I2C
|
|
ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
|
|
PMBUS_CMD_PAGE, 1, &chan, 1);
|
|
#else
|
|
struct udevice *dev;
|
|
|
|
ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev);
|
|
if (!ret)
|
|
ret = dm_i2c_write(dev, PMBUS_CMD_PAGE,
|
|
&chan, 1);
|
|
#endif
|
|
|
|
if (ret) {
|
|
printf("VID: failed to select VDD Page 0\n");
|
|
return ret;
|
|
}
|
|
|
|
/* Read the output voltage using PMBus command READ_VOUT */
|
|
#ifndef CONFIG_DM_I2C
|
|
ret = i2c_read(I2C_SVDD_MONITOR_ADDR,
|
|
PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
|
|
#else
|
|
dm_i2c_read(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, 2);
|
|
#endif
|
|
if (ret) {
|
|
printf("VID: failed to read the volatge\n");
|
|
return ret;
|
|
}
|
|
|
|
return vcode;
|
|
}
|
|
|
|
int set_serdes_volt(int svdd)
|
|
{
|
|
int ret, vdd_last;
|
|
u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND,
|
|
svdd & 0xFF, (svdd & 0xFF00) >> 8};
|
|
|
|
/* Write the desired voltage code to the SVDD regulator */
|
|
#ifndef CONFIG_DM_I2C
|
|
ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
|
|
PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
|
|
#else
|
|
struct udevice *dev;
|
|
|
|
ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev);
|
|
if (!ret)
|
|
ret = dm_i2c_write(dev, PMBUS_CMD_PAGE_PLUS_WRITE,
|
|
(void *)&buff, 5);
|
|
#endif
|
|
if (ret) {
|
|
printf("VID: I2C failed to write to the volatge regulator\n");
|
|
return -1;
|
|
}
|
|
|
|
/* Wait for the volatge to get to the desired value */
|
|
do {
|
|
vdd_last = get_serdes_volt();
|
|
if (vdd_last < 0) {
|
|
printf("VID: Couldn't read sensor abort VID adjust\n");
|
|
return -1;
|
|
}
|
|
} while (vdd_last != svdd);
|
|
|
|
return 1;
|
|
}
|
|
#else
|
|
int get_serdes_volt(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
int set_serdes_volt(int svdd)
|
|
{
|
|
int ret;
|
|
u8 brdcfg4;
|
|
|
|
printf("SVDD changing of RDB\n");
|
|
|
|
/* Read the BRDCFG54 via CLPD */
|
|
#ifndef CONFIG_DM_I2C
|
|
ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR,
|
|
QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
|
|
#else
|
|
struct udevice *dev;
|
|
|
|
ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev);
|
|
if (!ret)
|
|
ret = dm_i2c_read(dev, QIXIS_BRDCFG4_OFFSET,
|
|
(void *)&brdcfg4, 1);
|
|
#endif
|
|
|
|
if (ret) {
|
|
printf("VID: I2C failed to read the CPLD BRDCFG4\n");
|
|
return -1;
|
|
}
|
|
|
|
brdcfg4 = brdcfg4 | 0x08;
|
|
|
|
/* Write to the BRDCFG4 */
|
|
#ifndef CONFIG_DM_I2C
|
|
ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR,
|
|
QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
|
|
#else
|
|
ret = dm_i2c_write(dev, QIXIS_BRDCFG4_OFFSET,
|
|
(void *)&brdcfg4, 1);
|
|
#endif
|
|
|
|
if (ret) {
|
|
debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n");
|
|
return -1;
|
|
}
|
|
|
|
/* Wait for the volatge to get to the desired value */
|
|
udelay(10000);
|
|
|
|
return 1;
|
|
}
|
|
#endif
|
|
|
|
/* this function disables the SERDES, changes the SVDD Voltage and enables it*/
|
|
int board_adjust_vdd(int vdd)
|
|
{
|
|
int ret = 0;
|
|
|
|
debug("%s: vdd = %d\n", __func__, vdd);
|
|
|
|
/* Special settings to be performed when voltage is 900mV */
|
|
if (vdd == 900) {
|
|
ret = setup_serdes_volt(vdd);
|
|
if (ret < 0) {
|
|
ret = -1;
|
|
goto exit;
|
|
}
|
|
}
|
|
exit:
|
|
return ret;
|
|
}
|
|
|
|
#if !defined(CONFIG_SPL_BUILD)
|
|
int board_init(void)
|
|
{
|
|
init_final_memctl_regs();
|
|
#if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
|
|
u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
|
|
#endif
|
|
|
|
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
|
|
board_retimer_init();
|
|
|
|
#ifdef CONFIG_ENV_IS_NOWHERE
|
|
gd->env_addr = (ulong)&default_environment[0];
|
|
#endif
|
|
|
|
#if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
|
|
/* invert AQR105 IRQ pins polarity */
|
|
out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
|
|
#endif
|
|
|
|
#ifdef CONFIG_FSL_CAAM
|
|
sec_init();
|
|
#endif
|
|
#ifdef CONFIG_FSL_LS_PPA
|
|
ppa_init();
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
void detail_board_ddr_info(void)
|
|
{
|
|
puts("\nDDR ");
|
|
print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
|
|
print_ddr_info(0);
|
|
}
|
|
|
|
#if defined(CONFIG_ARCH_MISC_INIT)
|
|
int arch_misc_init(void)
|
|
{
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_FSL_MC_ENET
|
|
void board_quiesce_devices(void)
|
|
{
|
|
fsl_mc_ldpaa_exit(gd->bd);
|
|
}
|
|
|
|
void fdt_fixup_board_enet(void *fdt)
|
|
{
|
|
int offset;
|
|
|
|
offset = fdt_path_offset(fdt, "/fsl-mc");
|
|
|
|
if (offset < 0)
|
|
offset = fdt_path_offset(fdt, "/soc/fsl-mc");
|
|
|
|
if (offset < 0) {
|
|
printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
|
|
__func__, offset);
|
|
return;
|
|
}
|
|
|
|
if (get_mc_boot_status() == 0 &&
|
|
(is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
|
|
fdt_status_okay(fdt, offset);
|
|
else
|
|
fdt_status_fail(fdt, offset);
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_OF_BOARD_SETUP
|
|
void fsl_fdt_fixup_flash(void *fdt)
|
|
{
|
|
int offset;
|
|
#ifdef CONFIG_TFABOOT
|
|
u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
|
|
u32 val;
|
|
#endif
|
|
|
|
/*
|
|
* IFC-NOR and QSPI are muxed on SoC.
|
|
* So disable IFC node in dts if QSPI is enabled or
|
|
* disable QSPI node in dts in case QSPI is not enabled.
|
|
*/
|
|
|
|
#ifdef CONFIG_TFABOOT
|
|
enum boot_src src = get_boot_src();
|
|
bool disable_ifc = false;
|
|
|
|
switch (src) {
|
|
case BOOT_SOURCE_IFC_NOR:
|
|
disable_ifc = false;
|
|
break;
|
|
case BOOT_SOURCE_QSPI_NOR:
|
|
disable_ifc = true;
|
|
break;
|
|
default:
|
|
val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
|
|
if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
|
|
disable_ifc = true;
|
|
break;
|
|
}
|
|
|
|
if (disable_ifc) {
|
|
offset = fdt_path_offset(fdt, "/soc/ifc/nor");
|
|
|
|
if (offset < 0)
|
|
offset = fdt_path_offset(fdt, "/ifc/nor");
|
|
} else {
|
|
offset = fdt_path_offset(fdt, "/soc/quadspi");
|
|
|
|
if (offset < 0)
|
|
offset = fdt_path_offset(fdt, "/quadspi");
|
|
}
|
|
|
|
#else
|
|
#ifdef CONFIG_FSL_QSPI
|
|
offset = fdt_path_offset(fdt, "/soc/ifc/nor");
|
|
|
|
if (offset < 0)
|
|
offset = fdt_path_offset(fdt, "/ifc/nor");
|
|
#else
|
|
offset = fdt_path_offset(fdt, "/soc/quadspi");
|
|
|
|
if (offset < 0)
|
|
offset = fdt_path_offset(fdt, "/quadspi");
|
|
#endif
|
|
#endif
|
|
if (offset < 0)
|
|
return;
|
|
|
|
fdt_status_disabled(fdt, offset);
|
|
}
|
|
|
|
int ft_board_setup(void *blob, bd_t *bd)
|
|
{
|
|
int i;
|
|
u16 mc_memory_bank = 0;
|
|
|
|
u64 *base;
|
|
u64 *size;
|
|
u64 mc_memory_base = 0;
|
|
u64 mc_memory_size = 0;
|
|
u16 total_memory_banks;
|
|
|
|
ft_cpu_setup(blob, bd);
|
|
|
|
fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
|
|
|
|
if (mc_memory_base != 0)
|
|
mc_memory_bank++;
|
|
|
|
total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
|
|
|
|
base = calloc(total_memory_banks, sizeof(u64));
|
|
size = calloc(total_memory_banks, sizeof(u64));
|
|
|
|
/* fixup DT for the two GPP DDR banks */
|
|
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
|
|
base[i] = gd->bd->bi_dram[i].start;
|
|
size[i] = gd->bd->bi_dram[i].size;
|
|
}
|
|
|
|
#ifdef CONFIG_RESV_RAM
|
|
/* reduce size if reserved memory is within this bank */
|
|
if (gd->arch.resv_ram >= base[0] &&
|
|
gd->arch.resv_ram < base[0] + size[0])
|
|
size[0] = gd->arch.resv_ram - base[0];
|
|
else if (gd->arch.resv_ram >= base[1] &&
|
|
gd->arch.resv_ram < base[1] + size[1])
|
|
size[1] = gd->arch.resv_ram - base[1];
|
|
#endif
|
|
|
|
if (mc_memory_base != 0) {
|
|
for (i = 0; i <= total_memory_banks; i++) {
|
|
if (base[i] == 0 && size[i] == 0) {
|
|
base[i] = mc_memory_base;
|
|
size[i] = mc_memory_size;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
|
|
|
|
fdt_fsl_mc_fixup_iommu_map_entry(blob);
|
|
|
|
fsl_fdt_fixup_flash(blob);
|
|
|
|
#ifdef CONFIG_FSL_MC_ENET
|
|
fdt_fixup_board_enet(blob);
|
|
#endif
|
|
|
|
fdt_fixup_icid(blob);
|
|
|
|
if (is_pb_board())
|
|
fixup_ls1088ardb_pb_banner(blob);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
#endif /* defined(CONFIG_SPL_BUILD) */
|
|
|
|
#ifdef CONFIG_TFABOOT
|
|
#ifdef CONFIG_MTD_NOR_FLASH
|
|
int is_flash_available(void)
|
|
{
|
|
char *env_hwconfig = env_get("hwconfig");
|
|
enum boot_src src = get_boot_src();
|
|
int is_nor_flash_available = 1;
|
|
|
|
switch (src) {
|
|
case BOOT_SOURCE_IFC_NOR:
|
|
is_nor_flash_available = 1;
|
|
break;
|
|
case BOOT_SOURCE_QSPI_NOR:
|
|
is_nor_flash_available = 0;
|
|
break;
|
|
/*
|
|
* In Case of SD boot,if qspi is defined in env_hwconfig
|
|
* disable nor flash probe.
|
|
*/
|
|
default:
|
|
if (hwconfig_f("qspi", env_hwconfig))
|
|
is_nor_flash_available = 0;
|
|
break;
|
|
}
|
|
return is_nor_flash_available;
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
|
|
void *env_sf_get_env_addr(void)
|
|
{
|
|
return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
|
|
}
|
|
#endif
|
|
#endif
|