744 lines
17 KiB
C
744 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2017 NXP
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*/
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#include <common.h>
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#include <command.h>
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#include <env.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <asm/arch/fsl_serdes.h>
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#include <hwconfig.h>
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#include <fsl_mdio.h>
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#include <malloc.h>
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#include <phy.h>
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#include <fm_eth.h>
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#include <i2c.h>
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#include <miiphy.h>
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#include <fsl-mc/fsl_mc.h>
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#include <fsl-mc/ldpaa_wriop.h>
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#include "../common/qixis.h"
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#include "ls1088a_qixis.h"
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#ifdef CONFIG_FSL_MC_ENET
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#define SFP_TX 0
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/* - In LS1088A A there are only 16 SERDES lanes, spread across 2 SERDES banks.
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* Bank 1 -> Lanes A, B, C, D,
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* Bank 2 -> Lanes A,B, C, D,
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*/
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/* Mapping of 8 SERDES lanes to LS1088A QDS board slots. A value of '0' here
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* means that the mapping must be determined dynamically, or that the lane
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* maps to something other than a board slot.
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*/
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static u8 lane_to_slot_fsm1[] = {
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0, 0, 0, 0, 0, 0, 0, 0
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};
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/* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
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* housed.
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*/
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static int xqsgii_riser_phy_addr[] = {
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XQSGMII_CARD_PHY1_PORT0_ADDR,
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XQSGMII_CARD_PHY2_PORT0_ADDR,
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XQSGMII_CARD_PHY3_PORT0_ADDR,
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XQSGMII_CARD_PHY4_PORT0_ADDR,
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XQSGMII_CARD_PHY3_PORT2_ADDR,
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XQSGMII_CARD_PHY1_PORT2_ADDR,
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XQSGMII_CARD_PHY4_PORT2_ADDR,
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XQSGMII_CARD_PHY2_PORT2_ADDR,
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};
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static int sgmii_riser_phy_addr[] = {
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SGMII_CARD_PORT1_PHY_ADDR,
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SGMII_CARD_PORT2_PHY_ADDR,
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SGMII_CARD_PORT3_PHY_ADDR,
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SGMII_CARD_PORT4_PHY_ADDR,
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};
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/* Slot2 does not have EMI connections */
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#define EMI_NONE 0xFF
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#define EMI1_RGMII1 0
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#define EMI1_RGMII2 1
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#define EMI1_SLOT1 2
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static const char * const mdio_names[] = {
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"LS1088A_QDS_MDIO0",
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"LS1088A_QDS_MDIO1",
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"LS1088A_QDS_MDIO2",
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DEFAULT_WRIOP_MDIO2_NAME,
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};
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struct ls1088a_qds_mdio {
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u8 muxval;
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struct mii_dev *realbus;
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};
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struct reg_pair {
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uint addr;
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u8 *val;
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};
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static void sgmii_configure_repeater(int dpmac)
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{
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struct mii_dev *bus;
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uint8_t a = 0xf;
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int i, j, k, ret;
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unsigned short value;
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const char *dev = "LS1088A_QDS_MDIO2";
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int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
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int i2c_phy_addr = 0;
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int phy_addr = 0;
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uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
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uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
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uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
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uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
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u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};
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struct reg_pair reg_pair[10] = {
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{6, ®_val[0]}, {4, ®_val[1]},
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{8, ®_val[2]}, {0xf, NULL},
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{0x11, NULL}, {0x16, NULL},
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{0x18, NULL}, {0x23, ®_val[3]},
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{0x2d, ®_val[4]}, {4, ®_val[5]},
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};
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#ifdef CONFIG_DM_I2C
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struct udevice *udev;
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#endif
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/* Set I2c to Slot 1 */
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#ifndef CONFIG_DM_I2C
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ret = i2c_write(0x77, 0, 0, &a, 1);
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#else
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ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);
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if (!ret)
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ret = dm_i2c_write(udev, 0, &a, 1);
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#endif
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if (ret)
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goto error;
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switch (dpmac) {
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case 1:
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i2c_phy_addr = i2c_addr[1];
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phy_addr = 4;
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break;
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case 2:
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i2c_phy_addr = i2c_addr[0];
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phy_addr = 0;
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break;
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case 3:
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i2c_phy_addr = i2c_addr[3];
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phy_addr = 0xc;
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break;
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case 7:
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i2c_phy_addr = i2c_addr[2];
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phy_addr = 8;
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break;
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}
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/* Check the PHY status */
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ret = miiphy_set_current_dev(dev);
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if (ret > 0)
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goto error;
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bus = mdio_get_current_dev();
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debug("Reading from bus %s\n", bus->name);
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ret = miiphy_write(dev, phy_addr, 0x1f, 3);
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if (ret > 0)
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goto error;
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mdelay(10);
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ret = miiphy_read(dev, phy_addr, 0x11, &value);
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if (ret > 0)
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goto error;
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mdelay(10);
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if ((value & 0xfff) == 0x401) {
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miiphy_write(dev, phy_addr, 0x1f, 0);
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printf("DPMAC %d:PHY is ..... Configured\n", dpmac);
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return;
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}
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#ifdef CONFIG_DM_I2C
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i2c_get_chip_for_busnum(0, i2c_phy_addr, 1, &udev);
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#endif
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for (i = 0; i < 4; i++) {
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for (j = 0; j < 4; j++) {
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reg_pair[3].val = &ch_a_eq[i];
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reg_pair[4].val = &ch_a_ctl2[j];
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reg_pair[5].val = &ch_b_eq[i];
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reg_pair[6].val = &ch_b_ctl2[j];
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for (k = 0; k < 10; k++) {
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#ifndef CONFIG_DM_I2C
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ret = i2c_write(i2c_phy_addr,
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reg_pair[k].addr,
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1, reg_pair[k].val, 1);
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#else
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ret = i2c_get_chip_for_busnum(0,
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i2c_phy_addr,
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1, &udev);
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if (!ret)
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ret = dm_i2c_write(udev,
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reg_pair[k].addr,
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reg_pair[k].val, 1);
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#endif
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if (ret)
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goto error;
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}
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mdelay(100);
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ret = miiphy_read(dev, phy_addr, 0x11, &value);
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if (ret > 0)
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goto error;
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mdelay(100);
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ret = miiphy_read(dev, phy_addr, 0x11, &value);
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if (ret > 0)
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goto error;
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if ((value & 0xfff) == 0x401) {
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printf("DPMAC %d :PHY is configured ",
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dpmac);
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printf("after setting repeater 0x%x\n",
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value);
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i = 5;
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j = 5;
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} else {
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printf("DPMAC %d :PHY is failed to ",
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dpmac);
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printf("configure the repeater 0x%x\n", value);
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}
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}
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}
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miiphy_write(dev, phy_addr, 0x1f, 0);
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error:
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if (ret)
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printf("DPMAC %d ..... FAILED to configure PHY\n", dpmac);
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return;
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}
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static void qsgmii_configure_repeater(int dpmac)
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{
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uint8_t a = 0xf;
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int i, j, k;
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int i2c_phy_addr = 0;
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int phy_addr = 0;
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int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
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uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
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uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
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uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
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uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
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u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};
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struct reg_pair reg_pair[10] = {
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{6, ®_val[0]}, {4, ®_val[1]},
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{8, ®_val[2]}, {0xf, NULL},
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{0x11, NULL}, {0x16, NULL},
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{0x18, NULL}, {0x23, ®_val[3]},
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{0x2d, ®_val[4]}, {4, ®_val[5]},
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};
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const char *dev = mdio_names[EMI1_SLOT1];
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int ret = 0;
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unsigned short value;
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#ifdef CONFIG_DM_I2C
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struct udevice *udev;
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#endif
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/* Set I2c to Slot 1 */
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#ifndef CONFIG_DM_I2C
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ret = i2c_write(0x77, 0, 0, &a, 1);
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#else
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ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);
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if (!ret)
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ret = dm_i2c_write(udev, 0, &a, 1);
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#endif
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if (ret)
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goto error;
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switch (dpmac) {
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case 7:
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case 8:
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case 9:
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case 10:
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i2c_phy_addr = i2c_addr[2];
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phy_addr = 8;
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break;
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case 3:
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case 4:
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case 5:
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case 6:
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i2c_phy_addr = i2c_addr[3];
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phy_addr = 0xc;
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break;
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}
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/* Check the PHY status */
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ret = miiphy_set_current_dev(dev);
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ret = miiphy_write(dev, phy_addr, 0x1f, 3);
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mdelay(10);
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ret = miiphy_read(dev, phy_addr, 0x11, &value);
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mdelay(10);
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ret = miiphy_read(dev, phy_addr, 0x11, &value);
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mdelay(10);
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if ((value & 0xf) == 0xf) {
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miiphy_write(dev, phy_addr, 0x1f, 0);
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printf("DPMAC %d :PHY is ..... Configured\n", dpmac);
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return;
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}
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#ifdef CONFIG_DM_I2C
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i2c_get_chip_for_busnum(0, i2c_phy_addr, 1, &udev);
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#endif
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for (i = 0; i < 4; i++) {
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for (j = 0; j < 4; j++) {
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reg_pair[3].val = &ch_a_eq[i];
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reg_pair[4].val = &ch_a_ctl2[j];
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reg_pair[5].val = &ch_b_eq[i];
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reg_pair[6].val = &ch_b_ctl2[j];
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for (k = 0; k < 10; k++) {
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#ifndef CONFIG_DM_I2C
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ret = i2c_write(i2c_phy_addr,
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reg_pair[k].addr,
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1, reg_pair[k].val, 1);
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#else
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ret = i2c_get_chip_for_busnum(0,
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i2c_addr[dpmac],
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1, &udev);
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if (!ret)
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ret = dm_i2c_write(udev,
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reg_pair[k].addr,
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reg_pair[k].val, 1);
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#endif
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if (ret)
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goto error;
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}
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ret = miiphy_read(dev, phy_addr, 0x11, &value);
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if (ret > 0)
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goto error;
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mdelay(1);
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ret = miiphy_read(dev, phy_addr, 0x11, &value);
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if (ret > 0)
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goto error;
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mdelay(10);
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if ((value & 0xf) == 0xf) {
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miiphy_write(dev, phy_addr, 0x1f, 0);
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printf("DPMAC %d :PHY is ..... Configured\n",
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dpmac);
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return;
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}
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}
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}
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error:
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printf("DPMAC %d :PHY ..... FAILED to configure PHY\n", dpmac);
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return;
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}
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static const char *ls1088a_qds_mdio_name_for_muxval(u8 muxval)
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{
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return mdio_names[muxval];
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}
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struct mii_dev *mii_dev_for_muxval(u8 muxval)
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{
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struct mii_dev *bus;
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const char *name = ls1088a_qds_mdio_name_for_muxval(muxval);
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if (!name) {
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printf("No bus for muxval %x\n", muxval);
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return NULL;
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}
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bus = miiphy_get_dev_by_name(name);
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if (!bus) {
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printf("No bus by name %s\n", name);
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return NULL;
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}
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return bus;
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}
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static void ls1088a_qds_enable_SFP_TX(u8 muxval)
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{
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u8 brdcfg9;
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brdcfg9 = QIXIS_READ(brdcfg[9]);
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brdcfg9 &= ~BRDCFG9_SFPTX_MASK;
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brdcfg9 |= (muxval << BRDCFG9_SFPTX_SHIFT);
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QIXIS_WRITE(brdcfg[9], brdcfg9);
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}
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static void ls1088a_qds_mux_mdio(u8 muxval)
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{
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u8 brdcfg4;
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if (muxval <= 5) {
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brdcfg4 = QIXIS_READ(brdcfg[4]);
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brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
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brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
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QIXIS_WRITE(brdcfg[4], brdcfg4);
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}
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}
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static int ls1088a_qds_mdio_read(struct mii_dev *bus, int addr,
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int devad, int regnum)
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{
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struct ls1088a_qds_mdio *priv = bus->priv;
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ls1088a_qds_mux_mdio(priv->muxval);
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return priv->realbus->read(priv->realbus, addr, devad, regnum);
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}
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static int ls1088a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
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int regnum, u16 value)
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{
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struct ls1088a_qds_mdio *priv = bus->priv;
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ls1088a_qds_mux_mdio(priv->muxval);
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return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
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}
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static int ls1088a_qds_mdio_reset(struct mii_dev *bus)
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{
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struct ls1088a_qds_mdio *priv = bus->priv;
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return priv->realbus->reset(priv->realbus);
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}
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static int ls1088a_qds_mdio_init(char *realbusname, u8 muxval)
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{
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struct ls1088a_qds_mdio *pmdio;
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struct mii_dev *bus = mdio_alloc();
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if (!bus) {
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printf("Failed to allocate ls1088a_qds MDIO bus\n");
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return -1;
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}
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pmdio = malloc(sizeof(*pmdio));
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if (!pmdio) {
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printf("Failed to allocate ls1088a_qds private data\n");
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free(bus);
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return -1;
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}
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bus->read = ls1088a_qds_mdio_read;
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bus->write = ls1088a_qds_mdio_write;
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bus->reset = ls1088a_qds_mdio_reset;
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sprintf(bus->name, ls1088a_qds_mdio_name_for_muxval(muxval));
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pmdio->realbus = miiphy_get_dev_by_name(realbusname);
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if (!pmdio->realbus) {
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printf("No bus with name %s\n", realbusname);
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free(bus);
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free(pmdio);
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return -1;
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}
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pmdio->muxval = muxval;
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bus->priv = pmdio;
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return mdio_register(bus);
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}
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/*
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* Initialize the dpmac_info array.
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*
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*/
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static void initialize_dpmac_to_slot(void)
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{
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struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
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u32 serdes1_prtcl, cfg;
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cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
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FSL_CHASSIS3_SRDS1_PRTCL_MASK;
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cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
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serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
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switch (serdes1_prtcl) {
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case 0x12:
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printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
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serdes1_prtcl);
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lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
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lane_to_slot_fsm1[1] = EMI1_SLOT1 - 1;
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lane_to_slot_fsm1[2] = EMI1_SLOT1 - 1;
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lane_to_slot_fsm1[3] = EMI1_SLOT1 - 1;
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break;
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case 0x15:
|
|
case 0x1D:
|
|
printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
|
|
serdes1_prtcl);
|
|
lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
|
|
lane_to_slot_fsm1[1] = EMI1_SLOT1 - 1;
|
|
lane_to_slot_fsm1[2] = EMI_NONE;
|
|
lane_to_slot_fsm1[3] = EMI_NONE;
|
|
break;
|
|
case 0x1E:
|
|
printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
|
|
serdes1_prtcl);
|
|
lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
|
|
lane_to_slot_fsm1[1] = EMI1_SLOT1 - 1;
|
|
lane_to_slot_fsm1[2] = EMI1_SLOT1 - 1;
|
|
lane_to_slot_fsm1[3] = EMI_NONE;
|
|
break;
|
|
case 0x3A:
|
|
printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
|
|
serdes1_prtcl);
|
|
lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
|
|
lane_to_slot_fsm1[1] = EMI_NONE;
|
|
lane_to_slot_fsm1[2] = EMI1_SLOT1 - 1;
|
|
lane_to_slot_fsm1[3] = EMI1_SLOT1 - 1;
|
|
break;
|
|
|
|
default:
|
|
printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
|
|
__func__, serdes1_prtcl);
|
|
break;
|
|
}
|
|
}
|
|
|
|
void ls1088a_handle_phy_interface_sgmii(int dpmac_id)
|
|
{
|
|
struct mii_dev *bus;
|
|
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
|
|
u32 serdes1_prtcl, cfg;
|
|
|
|
cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
|
|
FSL_CHASSIS3_SRDS1_PRTCL_MASK;
|
|
cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
|
|
serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
|
|
|
|
int *riser_phy_addr;
|
|
char *env_hwconfig = env_get("hwconfig");
|
|
|
|
if (hwconfig_f("xqsgmii", env_hwconfig))
|
|
riser_phy_addr = &xqsgii_riser_phy_addr[0];
|
|
else
|
|
riser_phy_addr = &sgmii_riser_phy_addr[0];
|
|
|
|
switch (serdes1_prtcl) {
|
|
case 0x12:
|
|
case 0x15:
|
|
case 0x1E:
|
|
case 0x3A:
|
|
switch (dpmac_id) {
|
|
case 1:
|
|
wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[1]);
|
|
break;
|
|
case 2:
|
|
wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[0]);
|
|
break;
|
|
case 3:
|
|
wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[3]);
|
|
break;
|
|
case 7:
|
|
wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[2]);
|
|
break;
|
|
default:
|
|
printf("WRIOP: Wrong DPMAC%d set to SGMII", dpmac_id);
|
|
break;
|
|
}
|
|
break;
|
|
default:
|
|
printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
|
|
__func__, serdes1_prtcl);
|
|
return;
|
|
}
|
|
dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
|
|
bus = mii_dev_for_muxval(EMI1_SLOT1);
|
|
wriop_set_mdio(dpmac_id, bus);
|
|
}
|
|
|
|
void ls1088a_handle_phy_interface_qsgmii(int dpmac_id)
|
|
{
|
|
struct mii_dev *bus;
|
|
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
|
|
u32 serdes1_prtcl, cfg;
|
|
|
|
cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
|
|
FSL_CHASSIS3_SRDS1_PRTCL_MASK;
|
|
cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
|
|
serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
|
|
|
|
switch (serdes1_prtcl) {
|
|
case 0x1D:
|
|
case 0x1E:
|
|
switch (dpmac_id) {
|
|
case 3:
|
|
case 4:
|
|
case 5:
|
|
case 6:
|
|
wriop_set_phy_address(dpmac_id, 0, dpmac_id + 9);
|
|
break;
|
|
case 7:
|
|
case 8:
|
|
case 9:
|
|
case 10:
|
|
wriop_set_phy_address(dpmac_id, 0, dpmac_id + 1);
|
|
break;
|
|
}
|
|
|
|
dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
|
|
bus = mii_dev_for_muxval(EMI1_SLOT1);
|
|
wriop_set_mdio(dpmac_id, bus);
|
|
break;
|
|
default:
|
|
printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
|
|
serdes1_prtcl);
|
|
break;
|
|
}
|
|
}
|
|
|
|
void ls1088a_handle_phy_interface_xsgmii(int i)
|
|
{
|
|
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
|
|
u32 serdes1_prtcl, cfg;
|
|
|
|
cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
|
|
FSL_CHASSIS3_SRDS1_PRTCL_MASK;
|
|
cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
|
|
serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
|
|
|
|
switch (serdes1_prtcl) {
|
|
case 0x15:
|
|
case 0x1D:
|
|
case 0x1E:
|
|
wriop_set_phy_address(i, 0, i + 26);
|
|
ls1088a_qds_enable_SFP_TX(SFP_TX);
|
|
break;
|
|
default:
|
|
printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
|
|
serdes1_prtcl);
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void ls1088a_handle_phy_interface_rgmii(int dpmac_id)
|
|
{
|
|
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
|
|
u32 serdes1_prtcl, cfg;
|
|
struct mii_dev *bus;
|
|
|
|
cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
|
|
FSL_CHASSIS3_SRDS1_PRTCL_MASK;
|
|
cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
|
|
serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
|
|
|
|
switch (dpmac_id) {
|
|
case 4:
|
|
wriop_set_phy_address(dpmac_id, 0, RGMII_PHY1_ADDR);
|
|
dpmac_info[dpmac_id].board_mux = EMI1_RGMII1;
|
|
bus = mii_dev_for_muxval(EMI1_RGMII1);
|
|
wriop_set_mdio(dpmac_id, bus);
|
|
break;
|
|
case 5:
|
|
wriop_set_phy_address(dpmac_id, 0, RGMII_PHY2_ADDR);
|
|
dpmac_info[dpmac_id].board_mux = EMI1_RGMII2;
|
|
bus = mii_dev_for_muxval(EMI1_RGMII2);
|
|
wriop_set_mdio(dpmac_id, bus);
|
|
break;
|
|
default:
|
|
printf("qds: WRIOP: Unsupported RGMII SerDes Protocol 0x%02x\n",
|
|
serdes1_prtcl);
|
|
break;
|
|
}
|
|
}
|
|
#endif
|
|
|
|
int board_eth_init(bd_t *bis)
|
|
{
|
|
int error = 0, i;
|
|
#ifdef CONFIG_FSL_MC_ENET
|
|
struct memac_mdio_info *memac_mdio0_info;
|
|
char *env_hwconfig = env_get("hwconfig");
|
|
|
|
initialize_dpmac_to_slot();
|
|
|
|
memac_mdio0_info = (struct memac_mdio_info *)malloc(
|
|
sizeof(struct memac_mdio_info));
|
|
memac_mdio0_info->regs =
|
|
(struct memac_mdio_controller *)
|
|
CONFIG_SYS_FSL_WRIOP1_MDIO1;
|
|
memac_mdio0_info->name = DEFAULT_WRIOP_MDIO1_NAME;
|
|
|
|
/* Register the real MDIO1 bus */
|
|
fm_memac_mdio_init(bis, memac_mdio0_info);
|
|
/* Register the muxing front-ends to the MDIO buses */
|
|
ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_RGMII1);
|
|
ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_RGMII2);
|
|
ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1);
|
|
|
|
for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
|
|
switch (wriop_get_enet_if(i)) {
|
|
case PHY_INTERFACE_MODE_RGMII:
|
|
case PHY_INTERFACE_MODE_RGMII_ID:
|
|
ls1088a_handle_phy_interface_rgmii(i);
|
|
break;
|
|
case PHY_INTERFACE_MODE_QSGMII:
|
|
ls1088a_handle_phy_interface_qsgmii(i);
|
|
break;
|
|
case PHY_INTERFACE_MODE_SGMII:
|
|
ls1088a_handle_phy_interface_sgmii(i);
|
|
break;
|
|
case PHY_INTERFACE_MODE_XGMII:
|
|
ls1088a_handle_phy_interface_xsgmii(i);
|
|
break;
|
|
default:
|
|
break;
|
|
|
|
if (i == 16)
|
|
i = NUM_WRIOP_PORTS;
|
|
}
|
|
}
|
|
|
|
error = cpu_eth_init(bis);
|
|
|
|
if (hwconfig_f("xqsgmii", env_hwconfig)) {
|
|
for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
|
|
switch (wriop_get_enet_if(i)) {
|
|
case PHY_INTERFACE_MODE_QSGMII:
|
|
qsgmii_configure_repeater(i);
|
|
break;
|
|
case PHY_INTERFACE_MODE_SGMII:
|
|
sgmii_configure_repeater(i);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
if (i == 16)
|
|
i = NUM_WRIOP_PORTS;
|
|
}
|
|
}
|
|
#endif
|
|
error = pci_eth_init(bis);
|
|
return error;
|
|
}
|
|
|
|
#if defined(CONFIG_RESET_PHY_R)
|
|
void reset_phy(void)
|
|
{
|
|
mc_env_boot();
|
|
}
|
|
#endif /* CONFIG_RESET_PHY_R */
|