165 lines
5.3 KiB
Plaintext
165 lines
5.3 KiB
Plaintext
Overview
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--------
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The LS1028A Reference Design (RDB) is a high-performance computing,
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evaluation, and development platform that supports ARM SoC LS1028A and its
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derivatives.
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LS1028A SoC Overview
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--------------------------------------
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Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
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RDB Default Switch Settings (1: ON; 0: OFF)
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-------------------------------------------
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For XSPI NOR boot (default)
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SW2: 1111_1000
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SW3: 1111_0000
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SW5: 0011_1001
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For SD Boot
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SW2: 1000_1000
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SW3: 1111_0000
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SW5: 0011_1001
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For eMMC Boot
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SW2: 1001_1000
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SW3: 1111_0000
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SW5: 0011_1001
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LS1028ARDB board Overview
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-------------------------
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Processor
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Two Arm Cortex- A72 processor cores:
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- Based on 64-bit ARMv8 architecture
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- Up to 1.3 GHz operation
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- Single-threaded cores with 48 KB L1 instruction cache and 32 KB L1
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data cache
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- Arranged as a single cluster of two cores sharing a single 1 MB L2
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cache
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DDR memory
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- Five onboard 1G x8 discrete memory modules (Four data byte lanes
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ECC)
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- 32-bit data and 4-bit ECC
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- One chip select
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- Data transfer rates of up to 1.6 GT/s
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- Single-bit error correction and double-bit error detection ECC (4-bit
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check word across 32-bit data)
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High-speed serial ports(SerDes)
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- Lane 0: Supports one 1 GbE RJ45 SGMII, connected through the
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Qualcomm AR8033 PHY
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- Lane 1: Supports four 1.25 GbE RJ45 QSGMII, each connected
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through the NXP F104S8A PHY
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- Lane 2: Connects to one PCIe M.2 Key-E slot to support PCIe Gen3
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(8 Gbit/s) cards
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- Lane 3: Connects to one PCIe M.2 Key-E slot or one SATA M.2 Key-B
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slot through a register mux to support either PCIe Gen 3 (8 Gbit/s) or
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SATA Gen 3 cards (6 Gbit/s) at a time
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eSDHC
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- eSDHC1, eSDHC2
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SPI
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- Connects to two mikroBUS sockets to support mikro-click modules,
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such as Bluetooth 4.0, 2.4 GHz IEEE 802.15.4 radio transceiver, near
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field communications (NFC) controller
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Octal SPI (XSPI)
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- One 256 MB onboard XSPI serial NOR flash memory
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- One 512 MB onboard XSPI serial NAND flash memory
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- Supports a QSPI emulator for offboard QSPI emulation
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I2C
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- All system devices are accessed via I2C1, which is multiplexed on
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I2C multiplexer PCA9848 to isolate address conflicts and reduce
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capacitive load
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- I2C1 is used for EEPROMs, RTC, INA220 current-power sensor,
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thermal monitor, PCIe/SATA M.2 connectors and mikro-click modules
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1 and 2
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CAN
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- The two CAN DB9 ports can support CAN FD fast phase at data rates of
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up to 5 Mbit/s
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Serial audio interface(SAI)
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- Audio codec SGTL5000 provides headphone and audio LINEOUT for
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stereo speakers
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- IEEE1588 interface to support audio on SAI4
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QDS Default Switch Settings (1: ON; 0: OFF)
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-------------------------------------------
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For SD Boot
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SW1 : 1000_0000
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SW2 : 1110_0110
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SW3 : 0000_0010
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SW4 : 0000_0000
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SW5 : 0000_0000
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SW6 : 0000_0000
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SW7 : 1111_0011
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SW8 : 1110_0000
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SW9 : 1000_0001
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SW10: 1110_0000
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For XSPI Boot
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SW1 : 1111_0000
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SW2 : 0000_0110
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SW3 : 0000_0010
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SW4 : 0000_0000
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SW5 : 0110_0000
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SW6 : 0101_0000
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SW7 : 1111_0011
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SW8 : 1110_0000
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SW9 : 1000_0000
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SW10: 1110_0000
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LS1028AQDS board Overview
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-------------------------
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Processor
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Two Arm Cortex- A72 processor cores:
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- Based on 64-bit ARMv8 architecture
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- Up to 1.3 GHz operation
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- Single-threaded cores with 48 KB L1 instruction cache and 32 KB L1
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data cache
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- Arranged as a single cluster of two cores sharing a single 1 MB L2
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cache
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DDR memory
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- Supports data rates of up to 1.6 GT/s for both, DDR4 and DDR3L
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- Supports a single- or dual-ranked SODIMM or UDIMM connector
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- 32-bit data and 4-bit ECC
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- Supports x8/x16 devices
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- Supports ECC error detection and correction
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- 1.35 V or 1.2 V DDR power supply, with automatic tracking of VTT, to
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all devices in case of DDR3L or DDR4, respectively. Power can
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switch to 1.35 V or 1.2 V, based on the switch settings for DDR3L or
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DDR4 devices, respectively
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SerDes (Serializer/Deserializer)
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- Four-lane (0-3) SerDes:
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- Lane 0: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 10
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Gbit SXGMII, 1 Gbit SGMII
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- Lane 1: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 1 Gbit
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SGMII, 10 Gbit QXGMII, 5 Gbit QSGMII, 1 Gbit SGMII
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- Lane 2: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 1 Gbit
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SGMII
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- Lane 3: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 1 Gbit
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SGMII, SATA 2.0/3.0
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- Four slots on SerDes lanes support PCIe Gen1/2/3, 1 Gbit SGMII
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add-in cards
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- Lane 1 connects to a 2x10 connector with SFP+ through a retimer;
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lane 2 (TX lines) connects to an SMA connector
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Lane 3 connects to 1x7 header to support SATA devices
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eSDHC
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- eSDHC1, eSDHC2
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SPI
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- SPI1 and SPI2 support three onboard SPI flash memory devices:
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512 Mbit high-speed flash (with speed of up to 108/54 MHz)
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memory for storage
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4 Mbit low-speed flash memory (with speed of up to 40 MHz)
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64 Mbit high-speed flash memory (with speed of up to 104/80
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MHz)
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- SPI3 supports one onboard 64 Mbit SPI flash memory (with speed of
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up to 104/80 MHz)
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- All memories operate at 1.8 V
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- A header is provided on SPI1 to test SPI slave mode
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I2C
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- LS1028A supports eight I2C controllers
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Serial audio interface(SAI)
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Two SAI ports with audio codec SGTL5000:
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- Include stereo LINEIN with support for external analog input
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- Provide headphone and line output
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Display
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- DisplayPort connector to connect the DP data to a 4K display device
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(computer monitor)
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- eDP connector to connect the DP data to a 4K display panel
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