542 lines
11 KiB
C
542 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2006,2010 Freescale Semiconductor
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* Jeff Brown
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* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/io.h>
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#define pixis_base (u8 *)PIXIS_BASE
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/*
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* Simple board reset.
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*/
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void pixis_reset(void)
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{
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out_8(pixis_base + PIXIS_RST, 0);
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while (1);
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}
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/*
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* Per table 27, page 58 of MPC8641HPCN spec.
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*/
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static int set_px_sysclk(unsigned long sysclk)
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{
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u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux;
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switch (sysclk) {
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case 33:
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sysclk_s = 0x04;
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sysclk_r = 0x04;
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sysclk_v = 0x07;
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sysclk_aux = 0x00;
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break;
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case 40:
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sysclk_s = 0x01;
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sysclk_r = 0x1F;
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sysclk_v = 0x20;
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sysclk_aux = 0x01;
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break;
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case 50:
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sysclk_s = 0x01;
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sysclk_r = 0x1F;
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sysclk_v = 0x2A;
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sysclk_aux = 0x02;
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break;
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case 66:
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sysclk_s = 0x01;
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sysclk_r = 0x04;
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sysclk_v = 0x04;
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sysclk_aux = 0x03;
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break;
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case 83:
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sysclk_s = 0x01;
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sysclk_r = 0x1F;
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sysclk_v = 0x4B;
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sysclk_aux = 0x04;
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break;
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case 100:
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sysclk_s = 0x01;
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sysclk_r = 0x1F;
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sysclk_v = 0x5C;
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sysclk_aux = 0x05;
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break;
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case 134:
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sysclk_s = 0x06;
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sysclk_r = 0x1F;
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sysclk_v = 0x3B;
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sysclk_aux = 0x06;
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break;
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case 166:
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sysclk_s = 0x06;
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sysclk_r = 0x1F;
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sysclk_v = 0x4B;
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sysclk_aux = 0x07;
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break;
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default:
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printf("Unsupported SYSCLK frequency.\n");
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return 0;
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}
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vclkh = (sysclk_s << 5) | sysclk_r;
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vclkl = sysclk_v;
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out_8(pixis_base + PIXIS_VCLKH, vclkh);
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out_8(pixis_base + PIXIS_VCLKL, vclkl);
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out_8(pixis_base + PIXIS_AUX, sysclk_aux);
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return 1;
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}
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/* Set the CFG_SYSPLL bits
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*
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* This only has effect if PX_VCFGEN0[SYSPLL]=1, which is true if
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* read_from_px_regs() is called.
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*/
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static int set_px_mpxpll(unsigned long mpxpll)
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{
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switch (mpxpll) {
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case 2:
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case 4:
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case 6:
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case 8:
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case 10:
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case 12:
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case 14:
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case 16:
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clrsetbits_8(pixis_base + PIXIS_VSPEED1, 0x1F, mpxpll);
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return 1;
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}
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printf("Unsupported MPXPLL ratio.\n");
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return 0;
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}
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static int set_px_corepll(unsigned long corepll)
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{
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u8 val;
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switch (corepll) {
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case 20:
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val = 0x08;
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break;
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case 25:
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val = 0x0C;
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break;
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case 30:
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val = 0x10;
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break;
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case 35:
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val = 0x1C;
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break;
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case 40:
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val = 0x14;
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break;
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case 45:
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val = 0x0E;
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break;
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default:
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printf("Unsupported COREPLL ratio.\n");
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return 0;
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}
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clrsetbits_8(pixis_base + PIXIS_VSPEED0, 0x1F, val);
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return 1;
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}
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#ifndef CONFIG_SYS_PIXIS_VCFGEN0_ENABLE
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#define CONFIG_SYS_PIXIS_VCFGEN0_ENABLE 0x1C
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#endif
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/* Tell the PIXIS where to find the COREPLL, MPXPLL, SYSCLK values
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*
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* The PIXIS can be programmed to look at either the on-board dip switches
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* or various other PIXIS registers to determine the values for COREPLL,
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* MPXPLL, and SYSCLK.
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*
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* CONFIG_SYS_PIXIS_VCFGEN0_ENABLE is the value to write to the PIXIS_VCFGEN0
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* register that tells the pixis to use the various PIXIS register.
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*/
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static void read_from_px_regs(int set)
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{
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u8 tmp = in_8(pixis_base + PIXIS_VCFGEN0);
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if (set)
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tmp = tmp | CONFIG_SYS_PIXIS_VCFGEN0_ENABLE;
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else
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tmp = tmp & ~CONFIG_SYS_PIXIS_VCFGEN0_ENABLE;
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out_8(pixis_base + PIXIS_VCFGEN0, tmp);
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}
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/* CONFIG_SYS_PIXIS_VBOOT_ENABLE is the value to write to the PX_VCFGEN1
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* register that tells the pixis to use the PX_VBOOT[LBMAP] register.
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*/
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#ifndef CONFIG_SYS_PIXIS_VBOOT_ENABLE
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#define CONFIG_SYS_PIXIS_VBOOT_ENABLE 0x04
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#endif
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/* Configure the source of the boot location
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*
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* The PIXIS can be programmed to look at either the on-board dip switches
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* or the PX_VBOOT[LBMAP] register to determine where we should boot.
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*
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* If we want to boot from the alternate boot bank, we need to tell the PIXIS
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* to ignore the on-board dip switches and use the PX_VBOOT[LBMAP] instead.
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*/
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static void read_from_px_regs_altbank(int set)
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{
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u8 tmp = in_8(pixis_base + PIXIS_VCFGEN1);
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if (set)
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tmp = tmp | CONFIG_SYS_PIXIS_VBOOT_ENABLE;
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else
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tmp = tmp & ~CONFIG_SYS_PIXIS_VBOOT_ENABLE;
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out_8(pixis_base + PIXIS_VCFGEN1, tmp);
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}
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/* CONFIG_SYS_PIXIS_VBOOT_MASK contains the bits to set in VBOOT register that
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* tells the PIXIS what the alternate flash bank is.
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*
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* Note that it's not really a mask. It contains the actual LBMAP bits that
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* must be set to select the alternate bank. This code assumes that the
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* primary bank has these bits set to 0, and the alternate bank has these
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* bits set to 1.
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*/
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#ifndef CONFIG_SYS_PIXIS_VBOOT_MASK
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#define CONFIG_SYS_PIXIS_VBOOT_MASK (0x40)
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#endif
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/* Tell the PIXIS to boot from the default flash bank
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*
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* Program the default flash bank into the VBOOT register. This register is
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* used only if PX_VCFGEN1[FLASH]=1.
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*/
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static void clear_altbank(void)
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{
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clrbits_8(pixis_base + PIXIS_VBOOT, CONFIG_SYS_PIXIS_VBOOT_MASK);
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}
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/* Tell the PIXIS to boot from the alternate flash bank
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*
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* Program the alternate flash bank into the VBOOT register. This register is
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* used only if PX_VCFGEN1[FLASH]=1.
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*/
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static void set_altbank(void)
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{
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setbits_8(pixis_base + PIXIS_VBOOT, CONFIG_SYS_PIXIS_VBOOT_MASK);
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}
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/* Reset the board with watchdog disabled.
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*
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* This respects the altbank setting.
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*/
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static void set_px_go(void)
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{
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/* Disable the VELA sequencer and watchdog */
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clrbits_8(pixis_base + PIXIS_VCTL, 9);
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/* Reboot by starting the VELA sequencer */
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setbits_8(pixis_base + PIXIS_VCTL, 0x1);
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while (1);
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}
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/* Reset the board with watchdog enabled.
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*
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* This respects the altbank setting.
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*/
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static void set_px_go_with_watchdog(void)
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{
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/* Disable the VELA sequencer */
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clrbits_8(pixis_base + PIXIS_VCTL, 1);
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/* Enable the watchdog and reboot by starting the VELA sequencer */
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setbits_8(pixis_base + PIXIS_VCTL, 0x9);
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while (1);
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}
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/* Disable the watchdog
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*
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*/
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static int pixis_disable_watchdog_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
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char * const argv[])
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{
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/* Disable the VELA sequencer and the watchdog */
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clrbits_8(pixis_base + PIXIS_VCTL, 9);
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return 0;
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}
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U_BOOT_CMD(
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diswd, 1, 0, pixis_disable_watchdog_cmd,
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"Disable watchdog timer",
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""
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);
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#ifdef CONFIG_PIXIS_SGMII_CMD
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/* Enable or disable SGMII mode for a TSEC
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*/
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static int pixis_set_sgmii(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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int which_tsec = -1;
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unsigned char mask;
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unsigned char switch_mask;
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if ((argc > 2) && (strcmp(argv[1], "all") != 0))
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which_tsec = simple_strtoul(argv[1], NULL, 0);
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switch (which_tsec) {
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#ifdef CONFIG_TSEC1
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case 1:
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mask = PIXIS_VSPEED2_TSEC1SER;
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switch_mask = PIXIS_VCFGEN1_TSEC1SER;
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break;
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#endif
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#ifdef CONFIG_TSEC2
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case 2:
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mask = PIXIS_VSPEED2_TSEC2SER;
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switch_mask = PIXIS_VCFGEN1_TSEC2SER;
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break;
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#endif
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#ifdef CONFIG_TSEC3
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case 3:
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mask = PIXIS_VSPEED2_TSEC3SER;
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switch_mask = PIXIS_VCFGEN1_TSEC3SER;
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break;
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#endif
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#ifdef CONFIG_TSEC4
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case 4:
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mask = PIXIS_VSPEED2_TSEC4SER;
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switch_mask = PIXIS_VCFGEN1_TSEC4SER;
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break;
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#endif
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default:
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mask = PIXIS_VSPEED2_MASK;
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switch_mask = PIXIS_VCFGEN1_MASK;
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break;
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}
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/* Toggle whether the switches or FPGA control the settings */
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if (!strcmp(argv[argc - 1], "switch"))
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clrbits_8(pixis_base + PIXIS_VCFGEN1, switch_mask);
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else
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setbits_8(pixis_base + PIXIS_VCFGEN1, switch_mask);
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/* If it's not the switches, enable or disable SGMII, as specified */
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if (!strcmp(argv[argc - 1], "on"))
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clrbits_8(pixis_base + PIXIS_VSPEED2, mask);
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else if (!strcmp(argv[argc - 1], "off"))
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setbits_8(pixis_base + PIXIS_VSPEED2, mask);
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return 0;
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}
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U_BOOT_CMD(
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pixis_set_sgmii, CONFIG_SYS_MAXARGS, 1, pixis_set_sgmii,
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"pixis_set_sgmii"
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" - Enable or disable SGMII mode for a given TSEC \n",
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"\npixis_set_sgmii [TSEC num] <on|off|switch>\n"
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" TSEC num: 1,2,3,4 or 'all'. 'all' is default.\n"
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" on - enables SGMII\n"
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" off - disables SGMII\n"
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" switch - use switch settings"
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);
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#endif
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/*
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* This function takes the non-integral cpu:mpx pll ratio
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* and converts it to an integer that can be used to assign
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* FPGA register values.
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* input: strptr i.e. argv[2]
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*/
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static unsigned long strfractoint(char *strptr)
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{
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int i, j;
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int mulconst;
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int no_dec = 0;
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unsigned long intval = 0, decval = 0;
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char intarr[3], decarr[3];
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/* Assign the integer part to intarr[]
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* If there is no decimal point i.e.
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* if the ratio is an integral value
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* simply create the intarr.
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*/
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i = 0;
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while (strptr[i] != '.') {
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if (strptr[i] == 0) {
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no_dec = 1;
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break;
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}
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intarr[i] = strptr[i];
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i++;
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}
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intarr[i] = '\0';
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if (no_dec) {
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/* Currently needed only for single digit corepll ratios */
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mulconst = 10;
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decval = 0;
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} else {
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j = 0;
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i++; /* Skipping the decimal point */
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while ((strptr[i] >= '0') && (strptr[i] <= '9')) {
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decarr[j] = strptr[i];
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i++;
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j++;
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}
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decarr[j] = '\0';
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mulconst = 1;
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for (i = 0; i < j; i++)
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mulconst *= 10;
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decval = simple_strtoul(decarr, NULL, 10);
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}
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intval = simple_strtoul(intarr, NULL, 10);
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intval = intval * mulconst;
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return intval + decval;
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}
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static int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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unsigned int i;
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char *p_cf = NULL;
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char *p_cf_sysclk = NULL;
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char *p_cf_corepll = NULL;
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char *p_cf_mpxpll = NULL;
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char *p_altbank = NULL;
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char *p_wd = NULL;
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int unknown_param = 0;
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/*
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* No args is a simple reset request.
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*/
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if (argc <= 1) {
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pixis_reset();
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/* not reached */
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}
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for (i = 1; i < argc; i++) {
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if (strcmp(argv[i], "cf") == 0) {
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p_cf = argv[i];
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if (i + 3 >= argc) {
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break;
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}
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p_cf_sysclk = argv[i+1];
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p_cf_corepll = argv[i+2];
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p_cf_mpxpll = argv[i+3];
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i += 3;
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continue;
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}
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if (strcmp(argv[i], "altbank") == 0) {
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p_altbank = argv[i];
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continue;
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}
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if (strcmp(argv[i], "wd") == 0) {
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p_wd = argv[i];
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continue;
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}
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unknown_param = 1;
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}
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/*
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* Check that cf has all required parms
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*/
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if ((p_cf && !(p_cf_sysclk && p_cf_corepll && p_cf_mpxpll))
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|| unknown_param) {
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#ifdef CONFIG_SYS_LONGHELP
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puts(cmdtp->help);
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putc('\n');
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#endif
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return 1;
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}
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/*
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* PIXIS seems to be sensitive to the ordering of
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* the registers that are touched.
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*/
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read_from_px_regs(0);
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if (p_altbank)
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read_from_px_regs_altbank(0);
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clear_altbank();
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/*
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* Clock configuration specified.
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*/
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if (p_cf) {
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unsigned long sysclk;
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unsigned long corepll;
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unsigned long mpxpll;
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sysclk = simple_strtoul(p_cf_sysclk, NULL, 10);
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corepll = strfractoint(p_cf_corepll);
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mpxpll = simple_strtoul(p_cf_mpxpll, NULL, 10);
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if (!(set_px_sysclk(sysclk)
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&& set_px_corepll(corepll)
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&& set_px_mpxpll(mpxpll))) {
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#ifdef CONFIG_SYS_LONGHELP
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puts(cmdtp->help);
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putc('\n');
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#endif
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return 1;
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}
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read_from_px_regs(1);
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}
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/*
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* Altbank specified
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*
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* NOTE CHANGE IN BEHAVIOR: previous code would default
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* to enabling watchdog if altbank is specified.
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* Now the watchdog must be enabled explicitly using 'wd'.
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*/
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if (p_altbank) {
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set_altbank();
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read_from_px_regs_altbank(1);
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}
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/*
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* Reset with watchdog specified.
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*/
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if (p_wd)
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set_px_go_with_watchdog();
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else
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set_px_go();
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/*
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* Shouldn't be reached.
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*/
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return 0;
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}
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U_BOOT_CMD(
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pixis_reset, CONFIG_SYS_MAXARGS, 1, pixis_reset_cmd,
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"Reset the board using the FPGA sequencer",
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" pixis_reset\n"
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" pixis_reset [altbank]\n"
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" pixis_reset altbank wd\n"
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" pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
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" pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>"
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);
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