101 lines
3.2 KiB
Plaintext
101 lines
3.2 KiB
Plaintext
Overview
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=========
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C29XPCIE board is a series of Freescale PCIe add-in cards to perform
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as public key crypto accelerator or secure key management module.
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It includes C293PCIE board, C293PCIE board and C291PCIE board.
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The Freescale C29x family is a high performance crypto co-processor.
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It combines a single e500v2 core with necessary SEC engines.
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(maximum core frequency 1000/1200 MHz).
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The C29xPCIE board features are as follows:
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Memory subsystem:
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- 512Mbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus)
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- 64 Mbyte NOR flash single-chip memory
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- 4 Gbyte NAND flash memory
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- 1 Mbit AT24C1024 I2C EEPROM
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- 16 Mbyte SPI memory
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Interfaces:
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- 10/100/1000 BaseT Ethernet ports:
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- eTSEC1, RGMII: one 10/100/1000 port
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- eTSEC2, RGMII: one 10/100/1000 port
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- DUART interface:
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- DUART interface: supports two UARTs up to 115200 bps for
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console display
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Board connectors:
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- Mini-ITX power supply connector
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- JTAG/COP for debugging
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Physical Memory Map on C29xPCIE
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===============================
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Address Start Address End Memory type
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0x0_0000_0000 - 0x0_1fff_ffff 512MB DDR
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0xc_0000_0000 - 0xc_8fff_ffff 256MB PCIE memory
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0xf_ec00_0000 - 0xf_efff_ffff 64MB NOR flash
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0xf_ffb0_0000 - 0xf_ffb7_ffff 512KB SRAM
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0xf_ffc0_0000 - 0xf_ffc0_ffff 64KB PCIE IO
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0xf_ffdf_0000 - 0xf_ffdf_0fff 4KB CPLD
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0xf_ffe0_0000 - 0xf_ffef_ffff 1MB CCSR
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Serial Port Configuration on C29xPCIE
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=====================================
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Configure the serial port of the attached computer with the following values:
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-Data rate: 115200 bps
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-Number of data bits: 8
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-Parity: None
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-Number of Stop bits: 1
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-Flow Control: Hardware/None
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Settings of DIP-switch
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======================
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SW5[1:4]= 1111 and SW5[6]=0 for boot from 16bit NOR flash
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SW5[1:4]= 0110 and SW5[6]=0 for boot from SPI flash
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Note: 1 stands for 'off', 0 stands for 'on'
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Build and program U-Boot to NOR flash
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==================================
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1. Build u-boot.bin image example:
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export ARCH=powerpc
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export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
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make C293PCIE
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2. Program u-boot.bin into NOR flash
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=> tftp $loadaddr $uboot
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=> protect off eff40000 +$filesize
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=> erase eff40000 +$filesize
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=> cp.b $loadaddr eff40000 $filesize
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3. Check SW5[1:4]= 1111 and SW5[6]=0, then power on.
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Alternate NOR bank
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==================
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There are four banks in C29XPCIE board, example to change bank booting:
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1. Program u-boot.bin into alternate NOR bank
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=> tftp $loadaddr $uboot
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=> protect off e9f40000 +$filesize
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=> erase e9f40000 +$filesize
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=> cp.b $loadaddr e9f40000 $filesize
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2. Switch to alternate NOR bank
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=> cpld_cmd reset altbank [bank]
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- [bank] bank value select 1-4
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- bank 1 on the flash 0x0000000~0x0ffffff
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- bank 2 on the flash 0x1000000~0x1ffffff
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- bank 3 on the flash 0x2000000~0x2ffffff
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- bank 4 on the flash 0x3000000~0x3ffffff
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or set SW5[7]= ON/OFF and SW5[7]= ON/OFF, then power on again.
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Build and program U-Boot to SPI flash
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==================================
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1. Build u-boot-spi.bin image
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make C29xPCIE_SPIFLASH_config; make
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Need the boot_format tool to generate u-boot-spi.bin from the u-boot.bin.
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2. Program u-boot-spi.bin into SPI flash
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=> tftp $loadaddr $uboot-spi
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=> sf erase 0 100000
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=> sf write $loadaddr 0 $filesize
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3. Check SW5[1:4]= 0110 and SW5[6]=0, then power on.
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