119 lines
2.8 KiB
C
119 lines
2.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2007 - 2013 Tensilica Inc.
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* (C) Copyright 2014 - 2016 Cadence Design Systems Inc.
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*/
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#include <common.h>
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#include <command.h>
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#include <dm.h>
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#include <init.h>
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#include <dm/platform_data/net_ethoc.h>
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#include <env.h>
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#include <linux/ctype.h>
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#include <linux/string.h>
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#include <linux/stringify.h>
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#include <asm/global_data.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Check board idendity.
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* (Print information about the board to stdout.)
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*/
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#if defined(CONFIG_XTFPGA_LX60)
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const char *board = "XT_AV60";
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const char *description = "Avnet Xilinx LX60 FPGA Evaluation Board / ";
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#elif defined(CONFIG_XTFPGA_LX110)
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const char *board = "XT_AV110";
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const char *description = "Avnet Xilinx Virtex-5 LX110 Evaluation Kit / ";
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#elif defined(CONFIG_XTFPGA_LX200)
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const char *board = "XT_AV200";
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const char *description = "Avnet Xilinx Virtex-4 LX200 Evaluation Kit / ";
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#elif defined(CONFIG_XTFPGA_ML605)
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const char *board = "XT_ML605";
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const char *description = "Xilinx Virtex-6 FPGA ML605 Evaluation Kit / ";
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#elif defined(CONFIG_XTFPGA_KC705)
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const char *board = "XT_KC705";
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const char *description = "Xilinx Kintex-7 FPGA KC705 Evaluation Kit / ";
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#else
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const char *board = "<unknown>";
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const char *description = "";
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#endif
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int checkboard(void)
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{
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printf("Board: %s: %sTensilica bitstream\n", board, description);
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return 0;
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}
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int dram_init_banksize(void)
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{
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gd->bd->bi_memstart = PHYSADDR(CONFIG_SYS_SDRAM_BASE);
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gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
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return 0;
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}
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int board_postclk_init(void)
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{
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/*
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* Obtain CPU clock frequency from board and cache in global
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* data structure (Hz). Return 0 on success (OK to continue),
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* else non-zero (hang).
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*/
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#ifdef CONFIG_SYS_FPGAREG_FREQ
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gd->cpu_clk = (*(volatile unsigned long *)CONFIG_SYS_FPGAREG_FREQ);
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#else
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/* early Tensilica bitstreams lack this reg, but most run at 50 MHz */
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gd->cpu_clk = 50000000UL;
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#endif
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return 0;
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}
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/*
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* Miscellaneous late initializations.
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* The environment has been set up, so we can set the Ethernet address.
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*/
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int misc_init_r(void)
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{
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#ifdef CONFIG_CMD_NET
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/*
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* Initialize ethernet environment variables and board info.
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* Default MAC address comes from CONFIG_ETHADDR + DIP switches 1-6.
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*/
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char *s = env_get("ethaddr");
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if (s == 0) {
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unsigned int x;
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char s[] = __stringify(CONFIG_ETHBASE);
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x = (*(volatile u32 *)CONFIG_SYS_FPGAREG_DIPSW)
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& FPGAREG_MAC_MASK;
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sprintf(&s[15], "%02x", x);
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env_set("ethaddr", s);
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}
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#endif /* CONFIG_CMD_NET */
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return 0;
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}
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U_BOOT_DEVICE(sysreset) = {
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.name = "xtfpga_sysreset",
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};
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static struct ethoc_eth_pdata ethoc_pdata = {
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.eth_pdata = {
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.iobase = CONFIG_SYS_ETHOC_BASE,
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},
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.packet_base = CONFIG_SYS_ETHOC_BUFFER_ADDR,
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};
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U_BOOT_DEVICE(ethoc) = {
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.name = "ethoc",
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.platdata = ðoc_pdata,
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};
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