90 lines
2.9 KiB
C
90 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* mux.c
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*
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* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
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* Copyright (C) 2018 Robert Bosch Power Tools GmbH
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*/
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#include <common.h>
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#include <i2c.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/mux.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/io.h>
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#include "board.h"
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static struct module_pin_mux uart0_pin_mux[] = {
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{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},
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{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
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{-1},
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};
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static struct module_pin_mux i2c0_pin_mux[] = {
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{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
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{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
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{-1},
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};
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static struct module_pin_mux guardian_interfaces_pin_mux[] = {
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{OFFSET(mcasp0_ahclkx), (MODE(7) | PULLDOWN_EN)},
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{OFFSET(mcasp0_aclkx), (MODE(7) | PULLUP_EN)},
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{OFFSET(mii1_txd0), (MODE(7) | PULLUP_EN)},
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{OFFSET(uart1_rxd), (MODE(7) | RXACTIVE | PULLUDDIS)},
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{OFFSET(uart1_txd), (MODE(7) | PULLUDDIS)},
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{OFFSET(mii1_crs), (MODE(7) | PULLDOWN_EN)},
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{OFFSET(rmii1_refclk), (MODE(7) | PULLDOWN_EN)},
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{OFFSET(mii1_txd3), (MODE(7) | PULLUDDIS)},
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{OFFSET(mii1_rxdv), (MODE(7) | PULLDOWN_EN)},
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{-1},
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};
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#ifdef CONFIG_MTD_RAW_NAND
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static struct module_pin_mux nand_pin_mux[] = {
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{OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)},
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{OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)},
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{OFFSET(gpmc_ad2), (MODE(0) | PULLUDDIS | RXACTIVE)},
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{OFFSET(gpmc_ad3), (MODE(0) | PULLUDDIS | RXACTIVE)},
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{OFFSET(gpmc_ad4), (MODE(0) | PULLUDDIS | RXACTIVE)},
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{OFFSET(gpmc_ad5), (MODE(0) | PULLUDDIS | RXACTIVE)},
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{OFFSET(gpmc_ad6), (MODE(0) | PULLUDDIS | RXACTIVE)},
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{OFFSET(gpmc_ad7), (MODE(0) | PULLUDDIS | RXACTIVE)},
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#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
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{OFFSET(gpmc_ad8), (MODE(0) | PULLUDDIS | RXACTIVE)},
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{OFFSET(gpmc_ad9), (MODE(0) | PULLUDDIS | RXACTIVE)},
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{OFFSET(gpmc_ad10), (MODE(0) | PULLUDDIS | RXACTIVE)},
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{OFFSET(gpmc_ad11), (MODE(0) | PULLUDDIS | RXACTIVE)},
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{OFFSET(gpmc_ad12), (MODE(0) | PULLUDDIS | RXACTIVE)},
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{OFFSET(gpmc_ad13), (MODE(0) | PULLUDDIS | RXACTIVE)},
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{OFFSET(gpmc_ad14), (MODE(0) | PULLUDDIS | RXACTIVE)},
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{OFFSET(gpmc_ad15), (MODE(0) | PULLUDDIS | RXACTIVE)},
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#endif
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{OFFSET(gpmc_wait0), (MODE(0) | PULLUP_EN | RXACTIVE)},
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{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN)},
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{OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)},
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{OFFSET(gpmc_wen), (MODE(0) | PULLDOWN_EN)},
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{OFFSET(gpmc_oen_ren), (MODE(0) | PULLDOWN_EN)},
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{OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)},
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{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)},
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{-1},
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};
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#endif
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void enable_uart0_pin_mux(void)
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{
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configure_module_pin_mux(uart0_pin_mux);
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}
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void enable_i2c0_pin_mux(void)
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{
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configure_module_pin_mux(i2c0_pin_mux);
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}
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void enable_board_pin_mux(void)
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{
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#ifdef CONFIG_MTD_RAW_NAND
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configure_module_pin_mux(nand_pin_mux);
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#endif
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configure_module_pin_mux(guardian_interfaces_pin_mux);
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}
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