39 lines
738 B
Plaintext
39 lines
738 B
Plaintext
// SPDX-License-Identifier: GPL-2.0
|
|
/*
|
|
* Copyright (C) 2019 Intel Corporation <www.intel.com>
|
|
*
|
|
*/
|
|
|
|
/dts-v1/;
|
|
|
|
/ {
|
|
description = "FIT image with FPGA bistream";
|
|
#address-cells = <1>;
|
|
|
|
images {
|
|
fpga-periph-1 {
|
|
description = "FPGA peripheral bitstream";
|
|
data = /incbin/("../../../ghrd_10as066n2.periph.rbf");
|
|
type = "fpga";
|
|
arch = "arm";
|
|
compression = "none";
|
|
};
|
|
|
|
fpga-core-1 {
|
|
description = "FPGA core bitstream";
|
|
data = /incbin/("../../../ghrd_10as066n2.core.rbf");
|
|
type = "fpga";
|
|
arch = "arm";
|
|
compression = "none";
|
|
};
|
|
};
|
|
|
|
configurations {
|
|
default = "config-1";
|
|
config-1 {
|
|
description = "Boot with FPGA early IO release config";
|
|
fpga = "fpga-periph-1", "fpga-core-1";
|
|
};
|
|
};
|
|
};
|