164 lines
2.7 KiB
Plaintext
164 lines
2.7 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2018 Microsemi Corporation
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*/
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/dts-v1/;
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#include "mscc,ocelot_pcb.dtsi"
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#include <dt-bindings/mscc/ocelot_data.h>
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/ {
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model = "Ocelot PCB120 Reference Board";
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compatible = "mscc,ocelot-pcb120", "mscc,ocelot";
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chosen {
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stdout-path = "serial0:115200n8";
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};
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gpio-leds {
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compatible = "gpio-leds";
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poe_green {
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label = "pcb120:green:poe";
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gpios = <&sgpio 44 1>; /* p12.1 */
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default-state = "off";
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};
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poe_red {
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label = "pcb120:red:poe";
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gpios = <&sgpio 12 1>; /* p12.0 */
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default-state = "off";
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};
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alarm_green {
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label = "pcb120:green:alarm";
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gpios = <&sgpio 45 1>; /* p13.1 */
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default-state = "off";
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};
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alarm_red {
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label = "pcb120:red:alarm";
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gpios = <&sgpio 13 1>; /* p13.0 */
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default-state = "off";
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};
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dc_a_green {
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label = "pcb120:green:dc_a";
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gpios = <&sgpio 46 1>; /* p14.1 */
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default-state = "off";
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};
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dc_a_red {
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label = "pcb120:red:dc_a";
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gpios = <&sgpio 14 1>; /* p14.0 */
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default-state = "off";
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};
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dc_b_green {
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label = "pcb120:green:dc_b";
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gpios = <&sgpio 47 1>; /* p15.1 */
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default-state = "off";
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};
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dc_b_red {
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label = "pcb120:red:dc_b";
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gpios = <&sgpio 15 1>; /* p15.0 */
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default-state = "off";
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};
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status_green {
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label = "pcb120:green:status";
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gpios = <&sgpio 48 1>; /* p16.1 */
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default-state = "on";
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};
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status_red {
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label = "pcb120:red:alarm";
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gpios = <&sgpio 16 1>; /* p16.0 */
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default-state = "off";
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};
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};
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};
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&sgpio {
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status = "okay";
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mscc,sgpio-ports = <0x000FFFFF>;
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};
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&mdio0 {
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status = "okay";
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phy4: ethernet-phy@4 {
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reg = <3>;
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};
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phy5: ethernet-phy@5 {
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reg = <2>;
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};
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phy6: ethernet-phy@6 {
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reg = <1>;
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};
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phy7: ethernet-phy@7 {
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reg = <0>;
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};
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};
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&mdio1 {
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status = "okay";
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phy0: ethernet-phy@0 {
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reg = <3>;
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};
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phy1: ethernet-phy@1 {
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reg = <2>;
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};
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phy2: ethernet-phy@2 {
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reg = <1>;
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};
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phy3: ethernet-phy@3 {
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reg = <0>;
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};
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};
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&switch {
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ethernet-ports {
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port0: port@0 {
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reg = <5>;
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phy-handle = <&phy0>;
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phys = <&serdes_hsio 5 SERDES1G(2) PHY_MODE_SGMII>;
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};
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port1: port@1 {
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reg = <9>;
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phy-handle = <&phy1>;
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phys = <&serdes_hsio 9 SERDES1G(3) PHY_MODE_SGMII>;
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};
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port2: port@2 {
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reg = <6>;
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phy-handle = <&phy2>;
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phys = <&serdes_hsio 6 SERDES1G(4) PHY_MODE_SGMII>;
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};
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port3: port@3 {
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reg = <4>;
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phy-handle = <&phy3>;
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phys = <&serdes_hsio 4 SERDES1G(5) PHY_MODE_SGMII>;
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};
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port4: port@4 {
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reg = <3>;
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phy-handle = <&phy4>;
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};
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port5: port@5 {
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reg = <2>;
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phy-handle = <&phy5>;
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};
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port6: port@6 {
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reg = <1>;
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phy-handle = <&phy6>;
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};
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port7: port@7 {
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reg = <0>;
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phy-handle = <&phy7>;
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};
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};
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};
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