163 lines
3.6 KiB
C
163 lines
3.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/printk.h>
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#include <linux/psci.h>
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#include <linux/sizes.h>
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#include <asm/processor.h>
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#include <asm/psci.h>
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#include <asm/secure.h>
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#include "../debug.h"
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#include "../soc-info.h"
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#include "arm-mpcore.h"
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#include "cache-uniphier.h"
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#define UNIPHIER_SMPCTRL_ROM_RSV2 0x59801208
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void uniphier_smp_trampoline(void);
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void uniphier_smp_trampoline_end(void);
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u32 uniphier_smp_booted[CONFIG_ARMV7_PSCI_NR_CPUS];
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static int uniphier_get_nr_cpus(void)
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{
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switch (uniphier_get_soc_id()) {
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case UNIPHIER_PRO4_ID:
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case UNIPHIER_PRO5_ID:
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return 2;
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case UNIPHIER_PXS2_ID:
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case UNIPHIER_LD6B_ID:
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return 4;
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default:
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return 1;
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}
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}
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static void uniphier_smp_kick_all_cpus(void)
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{
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const u32 target_ways = BIT(0);
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size_t trmp_size;
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u32 trmp_src = (unsigned long)uniphier_smp_trampoline;
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u32 trmp_src_end = (unsigned long)uniphier_smp_trampoline_end;
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u32 trmp_dest, trmp_dest_end;
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int nr_cpus, i;
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int timeout = 1000;
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nr_cpus = uniphier_get_nr_cpus();
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if (nr_cpus == 1)
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return;
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for (i = 0; i < nr_cpus; i++) /* lock ways for all CPUs */
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uniphier_cache_set_active_ways(i, 0);
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uniphier_cache_inv_way(target_ways);
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uniphier_cache_enable();
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/* copy trampoline code */
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uniphier_cache_prefetch_range(trmp_src, trmp_src_end, target_ways);
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trmp_size = trmp_src_end - trmp_src;
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trmp_dest = trmp_src & (SZ_64K - 1);
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trmp_dest += SZ_1M - SZ_64K * 2;
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trmp_dest_end = trmp_dest + trmp_size;
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uniphier_cache_touch_range(trmp_dest, trmp_dest_end, target_ways);
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writel(trmp_dest, UNIPHIER_SMPCTRL_ROM_RSV2);
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asm("dsb ishst\n" /* Ensure the write to ROM_RSV2 is visible */
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"sev"); /* Bring up all secondary CPUs from Boot ROM into U-Boot */
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while (--timeout) {
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int all_booted = 1;
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for (i = 1; i < nr_cpus; i++)
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if (!uniphier_smp_booted[i])
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all_booted = 0;
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if (all_booted)
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break;
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udelay(1);
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/* barrier here because uniphier_smp_booted[] may be updated */
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cpu_relax();
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}
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if (!timeout)
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pr_warn("warning: some of secondary CPUs may not boot\n");
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uniphier_cache_disable();
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}
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void psci_board_init(void)
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{
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unsigned long scu_base;
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u32 scu_ctrl, tmp;
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asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (scu_base));
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scu_ctrl = readl(scu_base + 0x30);
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if (!(scu_ctrl & 1))
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writel(scu_ctrl | 0x1, scu_base + 0x30);
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scu_ctrl = readl(scu_base + SCU_CTRL);
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scu_ctrl |= SCU_ENABLE | SCU_STANDBY_ENABLE;
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writel(scu_ctrl, scu_base + SCU_CTRL);
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tmp = readl(scu_base + SCU_SNSAC);
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tmp |= 0xfff;
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writel(tmp, scu_base + SCU_SNSAC);
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uniphier_smp_kick_all_cpus();
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}
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void psci_arch_init(void)
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{
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u32 actlr;
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asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (actlr));
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actlr |= 0x41; /* set SMP and FW bits */
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asm("mcr p15, 0, %0, c1, c0, 1" : : "r" (actlr));
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}
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u32 uniphier_psci_holding_pen_release __secure_data = 0xffffffff;
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s32 __secure psci_cpu_on(u32 function_id, u32 cpuid, u32 entry_point,
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u32 context_id)
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{
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u32 cpu = cpuid & 0xff;
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debug_puts("[U-Boot PSCI] psci_cpu_on: cpuid=");
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debug_puth(cpuid);
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debug_puts(", entry_point=");
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debug_puth(entry_point);
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debug_puts(", context_id=");
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debug_puth(context_id);
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debug_puts("\n");
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psci_save(cpu, entry_point, context_id);
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/* We assume D-cache is off, so do not call flush_dcache() here */
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uniphier_psci_holding_pen_release = cpu;
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/* Send an event to wake up the secondary CPU. */
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asm("dsb ishst\n"
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"sev");
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return PSCI_RET_SUCCESS;
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}
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void __secure psci_system_reset(void)
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{
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reset_cpu(0);
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}
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