114 lines
3.1 KiB
C
114 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* emif4.c
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*
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* AM33XX emif4 configuration file
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*
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* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
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*/
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#include <common.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/ddr_defs.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/io.h>
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#include <asm/emif.h>
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static struct vtp_reg *vtpreg[2] = {
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(struct vtp_reg *)VTP0_CTRL_ADDR,
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(struct vtp_reg *)VTP1_CTRL_ADDR};
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#ifdef CONFIG_AM33XX
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static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
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#endif
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#ifdef CONFIG_AM43XX
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static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
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static struct cm_device_inst *cm_device =
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(struct cm_device_inst *)CM_DEVICE_INST;
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#endif
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#ifdef CONFIG_TI814X
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void config_dmm(const struct dmm_lisa_map_regs *regs)
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{
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struct dmm_lisa_map_regs *hw_lisa_map_regs =
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(struct dmm_lisa_map_regs *)DMM_BASE;
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enable_dmm_clocks();
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writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
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writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
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writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
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writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
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writel(regs->dmm_lisa_map_3, &hw_lisa_map_regs->dmm_lisa_map_3);
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writel(regs->dmm_lisa_map_2, &hw_lisa_map_regs->dmm_lisa_map_2);
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writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1);
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writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0);
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}
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#endif
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static void config_vtp(int nr)
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{
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writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE,
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&vtpreg[nr]->vtp0ctrlreg);
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writel(readl(&vtpreg[nr]->vtp0ctrlreg) & (~VTP_CTRL_START_EN),
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&vtpreg[nr]->vtp0ctrlreg);
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writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_START_EN,
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&vtpreg[nr]->vtp0ctrlreg);
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/* Poll for READY */
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while ((readl(&vtpreg[nr]->vtp0ctrlreg) & VTP_CTRL_READY) !=
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VTP_CTRL_READY)
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;
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}
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void __weak ddr_pll_config(unsigned int ddrpll_m)
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{
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}
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void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
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const struct ddr_data *data, const struct cmd_control *ctrl,
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const struct emif_regs *regs, int nr)
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{
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ddr_pll_config(pll);
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config_vtp(nr);
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config_cmd_ctrl(ctrl, nr);
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config_ddr_data(data, nr);
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#ifdef CONFIG_AM33XX
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config_io_ctrl(ioregs);
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/* Set CKE to be controlled by EMIF/DDR PHY */
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writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
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#endif
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#ifdef CONFIG_AM43XX
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writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl);
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while ((readl(&cm_device->cm_dll_ctrl) & CM_DLL_READYST) == 0)
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;
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config_io_ctrl(ioregs);
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/* Set CKE to be controlled by EMIF/DDR PHY */
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writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
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if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3)
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#ifndef CONFIG_SPL_RTC_DDR_SUPPORT
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/* Allow EMIF to control DDR_RESET */
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writel(0x00000000, &ddrctrl->ddrioctrl);
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#else
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/* Override EMIF DDR_RESET control */
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writel(0x80000000, &ddrctrl->ddrioctrl);
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#endif /* CONFIG_SPL_RTC_DDR_SUPPORT */
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#endif
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/* Program EMIF instance */
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config_ddr_phy(regs, nr);
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set_sdram_timings(regs, nr);
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if (get_emif_rev(EMIF1_BASE) == EMIF_4D5)
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config_sdram_emif4d5(regs, nr);
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else
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config_sdram(regs, nr);
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}
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