68 lines
1.2 KiB
ArmAsm
68 lines
1.2 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2018 NXP
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*/
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#include <config.h>
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#include <linux/linkage.h>
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#include <asm/armv7.h>
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#include <asm/psci.h>
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.pushsection ._secure.text, "ax"
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.arch_extension sec
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.globl v7_invalidate_l1
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v7_invalidate_l1:
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mov r0, #0
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mcr p15, 2, r0, c0, c0, 0
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mrc p15, 1, r0, c0, c0, 0
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movw r1, #0x7fff
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and r2, r1, r0, lsr #13
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movw r1, #0x3ff
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and r3, r1, r0, lsr #3 @ NumWays - 1
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add r2, r2, #1 @ NumSets
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and r0, r0, #0x7
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add r0, r0, #4 @ SetShift
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clz r1, r3 @ WayShift
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add r4, r3, #1 @ NumWays
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1:
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sub r2, r2, #1 @ NumSets--
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mov r3, r4 @ Temp = NumWays
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2:
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subs r3, r3, #1 @ Temp--
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mov r5, r3, lsl r1
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mov r6, r2, lsl r0
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orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
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mcr p15, 0, r5, c7, c6, 2
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bgt 2b
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cmp r2, #0
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bgt 1b
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dsb st
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isb
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mov pc, lr
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.globl psci_system_resume
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psci_system_resume:
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mov sp, r0
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/* invalidate L1 I-cache first */
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mov r6, #0x0
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mcr p15, 0, r6, c7, c5, 0
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mcr p15, 0, r6, c7, c5, 6
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/* enable the Icache and branch prediction */
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mov r6, #0x1800
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mcr p15, 0, r6, c1, c0, 0
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isb
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bl v7_invalidate_l1
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b imx_system_resume
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.popsection
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