152 lines
3.9 KiB
C
152 lines
3.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2015 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <asm/armv7.h>
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#include <asm/pl310.h>
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#include <asm/io.h>
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#include <asm/mach-imx/sys_proto.h>
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static void enable_ca7_smp(void)
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{
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u32 val;
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/* Read MIDR */
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asm volatile ("mrc p15, 0, %0, c0, c0, 0\n\t" : "=r"(val));
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val = (val >> 4);
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val &= 0xf;
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/* Only set the SMP for Cortex A7 */
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if (val == 0x7) {
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/* Read auxiliary control register */
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asm volatile ("mrc p15, 0, %0, c1, c0, 1\n\t" : "=r"(val));
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if (val & (1 << 6))
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return;
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/* Enable SMP */
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val |= (1 << 6);
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/* Write auxiliary control register */
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asm volatile ("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(val));
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DSB;
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ISB;
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}
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}
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#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
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void enable_caches(void)
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{
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#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
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enum dcache_option option = DCACHE_WRITETHROUGH;
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#else
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enum dcache_option option = DCACHE_WRITEBACK;
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#endif
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/* Avoid random hang when download by usb */
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invalidate_dcache_all();
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/* Set ACTLR.SMP bit for Cortex-A7 */
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enable_ca7_smp();
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/* Enable D-cache. I-cache is already enabled in start.S */
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dcache_enable();
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/* Enable caching on OCRAM and ROM */
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mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR,
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ROMCP_ARB_END_ADDR,
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option);
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mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR,
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IRAM_SIZE,
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option);
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}
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#else
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void enable_caches(void)
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{
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/*
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* Set ACTLR.SMP bit for Cortex-A7, even if the caches are
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* disabled by u-boot
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*/
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enable_ca7_smp();
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puts("WARNING: Caches not enabled\n");
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}
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#endif
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#ifndef CONFIG_SYS_L2CACHE_OFF
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#ifdef CONFIG_SYS_L2_PL310
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#define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002
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void v7_outer_cache_enable(void)
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{
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struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
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struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
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unsigned int val, cache_id;
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/*
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* Must disable the L2 before changing the latency parameters
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* and auxiliary control register.
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*/
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clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
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/*
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* Set bit 22 in the auxiliary control register. If this bit
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* is cleared, PL310 treats Normal Shared Non-cacheable
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* accesses as Cacheable no-allocate.
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*/
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setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE);
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if (is_mx6sl() || is_mx6sll()) {
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val = readl(&iomux->gpr[11]);
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if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
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/* L2 cache configured as OCRAM, reset it */
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val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
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writel(val, &iomux->gpr[11]);
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}
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}
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writel(0x132, &pl310->pl310_tag_latency_ctrl);
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writel(0x132, &pl310->pl310_data_latency_ctrl);
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val = readl(&pl310->pl310_prefetch_ctrl);
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/* Turn on the L2 I/D prefetch, double linefill */
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/* Set prefetch offset with any value except 23 as per errata 765569 */
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val |= 0x7000000f;
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/*
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* The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
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* The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL/SX/DQP
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* is r3p2.
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* But according to ARM PL310 errata: 752271
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* ID: 752271: Double linefill feature can cause data corruption
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* Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
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* Workaround: The only workaround to this erratum is to disable the
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* double linefill feature. This is the default behavior.
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*/
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cache_id = readl(&pl310->pl310_cache_id);
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if (((cache_id & L2X0_CACHE_ID_PART_MASK) == L2X0_CACHE_ID_PART_L310)
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&& ((cache_id & L2X0_CACHE_ID_RTL_MASK) < L2X0_CACHE_ID_RTL_R3P2))
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val &= ~(1 << 30);
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writel(val, &pl310->pl310_prefetch_ctrl);
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val = readl(&pl310->pl310_power_ctrl);
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val |= L2X0_DYNAMIC_CLK_GATING_EN;
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val |= L2X0_STNDBY_MODE_EN;
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writel(val, &pl310->pl310_power_ctrl);
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setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
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}
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void v7_outer_cache_disable(void)
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{
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struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
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clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
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}
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#endif /* !CONFIG_SYS_L2_PL310 */
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#endif /* !CONFIG_SYS_L2CACHE_OFF */
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