69 lines
1.1 KiB
Plaintext
69 lines
1.1 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* dts file for Xilinx ZynqMP Mini Configuration
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*
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* (C) Copyright 2018, Xilinx, Inc.
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*
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* Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
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*/
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/dts-v1/;
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/ {
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model = "ZynqMP MINI EMMC0";
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compatible = "xlnx,zynqmp";
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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serial0 = &dcc;
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mmc0 = &sdhci0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x20000000>;
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};
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dcc: dcc {
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compatible = "arm,dcc";
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status = "disabled";
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u-boot,dm-pre-reloc;
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};
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clk_xin: clk_xin {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <200000000>;
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};
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amba: amba {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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sdhci0: sdhci@ff160000 {
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u-boot,dm-pre-reloc;
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compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
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status = "disabled";
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reg = <0x0 0xff160000 0x0 0x1000>;
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clock-names = "clk_xin", "clk_ahb";
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clocks = <&clk_xin &clk_xin>;
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xlnx,device_id = <0>;
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};
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};
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};
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&dcc {
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status = "okay";
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};
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&sdhci0 {
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status = "okay";
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};
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