131 lines
2.0 KiB
Plaintext
131 lines
2.0 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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#include <dt-bindings/memory/stm32-sdram.h>
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/{
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soc {
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u-boot,dm-pre-reloc;
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fmc: fmc@A0000000 {
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compatible = "st,stm32-fmc";
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reg = <0xA0000000 0x1000>;
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clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>;
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pinctrl-0 = <&fmc_pins>;
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pinctrl-names = "default";
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status = "okay";
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u-boot,dm-pre-reloc;
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};
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mac: ethernet@40028000 {
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compatible = "st,stm32-dwmac";
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reg = <0x40028000 0x8000>;
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reg-names = "stmmaceth";
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clocks = <&rcc 0 STM32F7_AHB1_CLOCK(ETHMAC)>,
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<&rcc 0 STM32F7_AHB1_CLOCK(ETHMACTX)>,
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<&rcc 0 STM32F7_AHB1_CLOCK(ETHMACRX)>;
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interrupts = <61>, <62>;
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interrupt-names = "macirq", "eth_wake_irq";
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snps,pbl = <8>;
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snps,mixed-burst;
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dma-ranges;
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pinctrl-0 = <ðernet_mii>;
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phy-mode = "rmii";
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phy-handle = <&phy0>;
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status = "okay";
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mdio0 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dwmac-mdio";
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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};
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};
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qspi: quadspi@A0001000 {
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compatible = "st,stm32f469-qspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;
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reg-names = "qspi", "qspi_mm";
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interrupts = <92>;
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spi-max-frequency = <108000000>;
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clocks = <&rcc 0 STM32F7_AHB3_CLOCK(QSPI)>;
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resets = <&rcc STM32F7_AHB3_RESET(QSPI)>;
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pinctrl-0 = <&qspi_pins>;
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status = "okay";
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};
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};
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};
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&clk_hse {
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u-boot,dm-pre-reloc;
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};
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&gpioa {
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u-boot,dm-pre-reloc;
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};
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&gpiob {
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u-boot,dm-pre-reloc;
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};
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&gpioc {
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u-boot,dm-pre-reloc;
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};
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&gpiod {
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u-boot,dm-pre-reloc;
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};
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&gpioe {
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u-boot,dm-pre-reloc;
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};
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&gpiof {
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u-boot,dm-pre-reloc;
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};
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&gpiog {
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u-boot,dm-pre-reloc;
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};
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&gpioh {
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u-boot,dm-pre-reloc;
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};
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&gpioi {
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u-boot,dm-pre-reloc;
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};
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&pinctrl {
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u-boot,dm-pre-reloc;
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fmc_pins: fmc@0 {
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u-boot,dm-pre-reloc;
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pins
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{
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u-boot,dm-pre-reloc;
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};
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};
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};
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&pwrcfg {
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u-boot,dm-pre-reloc;
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};
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&rcc {
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u-boot,dm-pre-reloc;
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};
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&timer5 {
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u-boot,dm-pre-reloc;
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};
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&usart1 {
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u-boot,dm-pre-reloc;
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clocks = <&rcc 0 STM32F7_APB2_CLOCK(USART1)>;
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};
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