734 lines
13 KiB
Plaintext
734 lines
13 KiB
Plaintext
menuconfig ELBC_BR4_OR4
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bool "ELBC BR4/OR4"
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if ELBC_BR4_OR4
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config BR4_OR4_NAME
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string "Identifier"
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config BR4_OR4_BASE
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hex "Port base"
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choice
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prompt "Port size"
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config BR4_PORTSIZE_8BIT
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bool "8-bit"
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config BR4_PORTSIZE_16BIT
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depends on !BR4_MACHINE_FCM
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bool "16-bit"
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config BR4_PORTSIZE_32BIT
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depends on !BR4_MACHINE_FCM
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depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379
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bool "32-bit"
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endchoice
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if BR4_MACHINE_FCM
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choice
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prompt "Data Error Checking"
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config BR4_ERRORCHECKING_DISABLED
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bool "Disabled"
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config BR4_ERRORCHECKING_ECC_CHECKING
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bool "ECC checking / No ECC generation"
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config BR4_ERRORCHECKING_BOTH
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bool "ECC checking and generation"
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endchoice
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endif
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config BR4_WRITE_PROTECT
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bool "Write-protect"
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config BR4_MACHINE_UPM
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bool
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choice
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prompt "Machine select"
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config BR4_MACHINE_GPCM
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bool "GPCM"
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config BR4_MACHINE_FCM
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depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360
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bool "FCM"
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config BR4_MACHINE_SDRAM
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depends on ARCH_MPC8349 || ARCH_MPC8360
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bool "SDRAM"
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config BR4_MACHINE_UPMA
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select BR4_MACHINE_UPM
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bool "UPM (A)"
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config BR4_MACHINE_UPMB
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select BR4_MACHINE_UPM
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bool "UPM (B)"
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config BR4_MACHINE_UPMC
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select BR4_MACHINE_UPM
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bool "UPM (C)"
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endchoice
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if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360
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choice
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prompt "Atomic operations"
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config BR4_ATOMIC_NONE
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bool "No atomic operations"
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config BR4_ATOMIC_RAWA
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bool "Read-after-write-atomic"
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config BR4_ATOMIC_WARA
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bool "Write-after-read-atomic"
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endchoice
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endif
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if BR4_MACHINE_GPCM || BR4_MACHINE_FCM || BR4_MACHINE_UPM || BR4_MACHINE_SDRAM
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choice
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prompt "Address mask"
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config OR4_AM_32_KBYTES
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depends on !BR4_MACHINE_SDRAM
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bool "32 kb"
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config OR4_AM_64_KBYTES
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bool "64 kb"
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config OR4_AM_128_KBYTES
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bool "128 kb"
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config OR4_AM_256_KBYTES
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bool "256 kb"
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config OR4_AM_512_KBYTES
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bool "512 kb"
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config OR4_AM_1_MBYTES
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bool "1 mb"
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config OR4_AM_2_MBYTES
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bool "2 mb"
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config OR4_AM_4_MBYTES
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bool "4 mb"
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config OR4_AM_8_MBYTES
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bool "8 mb"
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config OR4_AM_16_MBYTES
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bool "16 mb"
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config OR4_AM_32_MBYTES
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bool "32 mb"
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config OR4_AM_64_MBYTES
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bool "64 mb"
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# XXX: Some boards define 128MB AM with GPCM, even though it should not be
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# possible according to the manuals
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config OR4_AM_128_MBYTES
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bool "128 mb"
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# XXX: Some boards define 256MB AM with GPCM, even though it should not be
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# possible according to the manuals
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config OR4_AM_256_MBYTES
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bool "256 mb"
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config OR4_AM_512_MBYTES
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depends on BR4_MACHINE_FCM
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bool "512 mb"
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# XXX: Some boards define 1GB AM with GPCM, even though it should not be
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# possible according to the manuals
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config OR4_AM_1_GBYTES
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bool "1 gb"
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config OR4_AM_2_GBYTES
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depends on BR4_MACHINE_FCM
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bool "2 gb"
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config OR4_AM_4_GBYTES
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depends on BR4_MACHINE_FCM
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bool "4 gb"
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endchoice
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config OR4_XAM_SET
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bool "Set unused bytes after address mask"
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choice
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prompt "Buffer control disable"
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config OR4_BCTLD_ASSERTED
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bool "Asserted"
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config OR4_BCTLD_NOT_ASSERTED
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bool "Not asserted"
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endchoice
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endif
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if BR4_MACHINE_GPCM || BR4_MACHINE_FCM
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choice
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prompt "Cycle length in bus clocks"
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config OR4_SCY_0
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bool "No wait states"
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config OR4_SCY_1
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bool "1 wait state"
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config OR4_SCY_2
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bool "2 wait states"
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config OR4_SCY_3
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bool "3 wait states"
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config OR4_SCY_4
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bool "4 wait states"
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config OR4_SCY_5
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bool "5 wait states"
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config OR4_SCY_6
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bool "6 wait states"
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config OR4_SCY_7
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bool "7 wait states"
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config OR4_SCY_8
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depends on BR4_MACHINE_GPCM
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bool "8 wait states"
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config OR4_SCY_9
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depends on BR4_MACHINE_GPCM
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bool "9 wait states"
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config OR4_SCY_10
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depends on BR4_MACHINE_GPCM
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bool "10 wait states"
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config OR4_SCY_11
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depends on BR4_MACHINE_GPCM
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bool "11 wait states"
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config OR4_SCY_12
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depends on BR4_MACHINE_GPCM
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bool "12 wait states"
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config OR4_SCY_13
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depends on BR4_MACHINE_GPCM
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bool "13 wait states"
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config OR4_SCY_14
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depends on BR4_MACHINE_GPCM
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bool "14 wait states"
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config OR4_SCY_15
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depends on BR4_MACHINE_GPCM
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bool "15 wait states"
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endchoice
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endif # BR4_MACHINE_GPCM || BR4_MACHINE_FCM
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if BR4_MACHINE_GPCM
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choice
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prompt "Chip select negotiation time"
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config OR4_CSNT_NORMAL
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bool "Normal"
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config OR4_CSNT_EARLIER
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bool "Earlier"
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endchoice
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choice
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prompt "Address to chip-select setup"
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config OR4_ACS_SAME_TIME
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bool "At the same time"
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config OR4_ACS_HALF_CYCLE_EARLIER
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bool "Half of a bus clock cycle earlier"
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config OR4_ACS_QUARTER_CYCLE_EARLIER
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bool "Half/Quarter of a bus clock cycle earlier"
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endchoice
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choice
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prompt "Extra address to check-select setup"
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config OR4_XACS_NORMAL
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bool "Normal"
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config OR4_XACS_EXTENDED
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bool "Extended"
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endchoice
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choice
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prompt "External address termination"
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config OR4_SETA_INTERNAL
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bool "Access is terminated internally"
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config OR4_SETA_EXTERNAL
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bool "Access is terminated externally"
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endchoice
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endif # BR4_MACHINE_GPCM
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if BR4_MACHINE_FCM
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choice
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prompt "NAND Flash EEPROM page size"
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config OR4_PGS_SMALL
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bool "Small page device"
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config OR4_PGS_LARGE
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bool "Large page device"
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endchoice
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choice
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prompt "Chip select to command time"
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config OR4_CSCT_1_CYCLE
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depends on OR4_TRLX_NORMAL
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bool "1 cycle"
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config OR4_CSCT_2_CYCLE
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depends on OR4_TRLX_RELAXED
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bool "2 cycles"
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config OR4_CSCT_4_CYCLE
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depends on OR4_TRLX_NORMAL
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bool "4 cycles"
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config OR4_CSCT_8_CYCLE
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depends on OR4_TRLX_RELAXED
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bool "8 cycles"
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endchoice
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choice
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prompt "Command setup time"
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config OR4_CST_COINCIDENT
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depends on OR4_TRLX_NORMAL
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bool "Coincident with any command"
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config OR4_CST_QUARTER_CLOCK
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depends on OR4_TRLX_NORMAL
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bool "0.25 clocks after"
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config OR4_CST_HALF_CLOCK
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depends on OR4_TRLX_RELAXED
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bool "0.5 clocks after"
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config OR4_CST_ONE_CLOCK
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depends on OR4_TRLX_RELAXED
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bool "1 clock after"
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endchoice
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choice
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prompt "Command hold time"
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config OR4_CHT_HALF_CLOCK
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depends on OR4_TRLX_NORMAL
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bool "0.5 clocks before"
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config OR4_CHT_ONE_CLOCK
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depends on OR4_TRLX_NORMAL
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bool "1 clock before"
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config OR4_CHT_ONE_HALF_CLOCK
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depends on OR4_TRLX_RELAXED
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bool "1.5 clocks before"
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config OR4_CHT_TWO_CLOCK
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depends on OR4_TRLX_RELAXED
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bool "2 clocks before"
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endchoice
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choice
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prompt "Reset setup time"
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config OR4_RST_THREE_QUARTER_CLOCK
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depends on OR4_TRLX_NORMAL
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bool "0.75 clocks prior"
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config OR4_RST_ONE_HALF_CLOCK
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depends on OR4_TRLX_RELAXED
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bool "0.5 clocks prior"
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config OR4_RST_ONE_CLOCK
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bool "1 clock prior"
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endchoice
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endif # BR4_MACHINE_FCM
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if BR4_MACHINE_UPM
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choice
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prompt "Burst inhibit"
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config OR4_BI_BURSTSUPPORT
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bool "Support burst access"
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config OR4_BI_BURSTINHIBIT
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bool "Inhibit burst access"
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endchoice
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endif # BR4_MACHINE_UPM
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if BR4_MACHINE_SDRAM
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choice
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prompt "Number of column address lines"
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config OR4_COLS_7
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bool "7"
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config OR4_COLS_8
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bool "8"
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config OR4_COLS_9
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bool "9"
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config OR4_COLS_10
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bool "10"
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config OR4_COLS_11
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bool "11"
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config OR4_COLS_12
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bool "12"
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config OR4_COLS_13
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bool "13"
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config OR4_COLS_14
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bool "14"
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endchoice
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choice
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prompt "Number of rows address lines"
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config OR4_ROWS_9
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bool "9"
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config OR4_ROWS_10
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bool "10"
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config OR4_ROWS_11
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bool "11"
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config OR4_ROWS_12
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bool "12"
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config OR4_ROWS_13
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bool "13"
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config OR4_ROWS_14
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bool "14"
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config OR4_ROWS_15
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bool "15"
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endchoice
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choice
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prompt "Page mode select"
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config OR4_PMSEL_BTB
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bool "Back-to-back"
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config OR4_PMSEL_KEPT_OPEN
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bool "Page kept open until page miss or refresh"
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endchoice
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endif # BR4_MACHINE_SDRAM
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choice
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prompt "Relaxed timing"
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config OR4_TRLX_NORMAL
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bool "Normal"
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config OR4_TRLX_RELAXED
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bool "Relaxed"
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endchoice
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choice
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prompt "Extended hold time"
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config OR4_EHTR_NORMAL
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depends on OR4_TRLX_NORMAL
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bool "Normal"
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config OR4_EHTR_1_CYCLE
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depends on OR4_TRLX_NORMAL
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bool "1 idle clock cycle inserted"
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config OR4_EHTR_4_CYCLE
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depends on OR4_TRLX_RELAXED
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bool "4 idle clock cycles inserted"
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config OR4_EHTR_8_CYCLE
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depends on OR4_TRLX_RELAXED
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bool "8 idle clock cycles inserted"
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endchoice
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if !ARCH_MPC8308
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choice
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prompt "External address latch delay"
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config OR4_EAD_NONE
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bool "None"
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config OR4_EAD_EXTRA
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bool "Extra"
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endchoice
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endif # !ARCH_MPC8308
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endif # ELBC_BR4_OR4
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config BR4_PORTSIZE
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hex
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default 0x800 if BR4_PORTSIZE_8BIT
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default 0x1000 if BR4_PORTSIZE_16BIT
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default 0x1800 if BR4_PORTSIZE_32BIT
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config BR4_ERRORCHECKING
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hex
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default 0x0 if !BR4_MACHINE_FCM
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default 0x0 if BR4_ERRORCHECKING_DISABLED
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default 0x200 if BR4_ERRORCHECKING_ECC_CHECKING
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default 0x400 if BR4_ERRORCHECKING_BOTH
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config BR4_WRITE_PROTECT_BIT
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hex
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default 0x0 if !BR4_WRITE_PROTECT
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default 0x100 if BR4_WRITE_PROTECT
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config BR4_MACHINE
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hex
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default 0x0 if BR4_MACHINE_GPCM
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default 0x20 if BR4_MACHINE_FCM
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default 0x60 if BR4_MACHINE_SDRAM
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default 0x80 if BR4_MACHINE_UPMA
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default 0xa0 if BR4_MACHINE_UPMB
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default 0xc0 if BR4_MACHINE_UPMC
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config BR4_ATOMIC
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hex
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default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360
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default 0x0 if BR4_ATOMIC_NONE
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default 0x4 if BR4_ATOMIC_RAWA
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default 0x8 if BR4_ATOMIC_WARA
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config BR4_VALID_BIT
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hex
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default 0x0 if !ELBC_BR4_OR4
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default 0x1 if ELBC_BR4_OR4
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config OR4_AM
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hex
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default 0xffff8000 if OR4_AM_32_KBYTES && !BR4_MACHINE_SDRAM
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default 0xffff0000 if OR4_AM_64_KBYTES
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default 0xfffe0000 if OR4_AM_128_KBYTES
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default 0xfffc0000 if OR4_AM_256_KBYTES
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default 0xfff80000 if OR4_AM_512_KBYTES
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default 0xfff00000 if OR4_AM_1_MBYTES
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default 0xffe00000 if OR4_AM_2_MBYTES
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default 0xffc00000 if OR4_AM_4_MBYTES
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default 0xff800000 if OR4_AM_8_MBYTES
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default 0xff000000 if OR4_AM_16_MBYTES
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default 0xfe000000 if OR4_AM_32_MBYTES
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default 0xfc000000 if OR4_AM_64_MBYTES
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default 0xf8000000 if OR4_AM_128_MBYTES
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default 0xf0000000 if OR4_AM_256_MBYTES
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default 0xe0000000 if OR4_AM_512_MBYTES
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default 0xc0000000 if OR4_AM_1_GBYTES
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default 0x80000000 if OR4_AM_2_GBYTES
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default 0x00000000 if OR4_AM_4_GBYTES
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config OR4_XAM
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hex
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default 0x0 if !OR4_XAM_SET
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default 0x6000 if OR4_XAM_SET
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config OR4_BCTLD
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hex
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default 0x0 if OR4_BCTLD_ASSERTED
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default 0x1000 if OR4_BCTLD_NOT_ASSERTED
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config OR4_BI
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hex
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default 0x0 if !BR4_MACHINE_UPM
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default 0x0 if OR4_BI_BURSTSUPPORT
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default 0x100 if OR4_BI_BURSTINHIBIT
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config OR4_COLS
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hex
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default 0x0 if !BR4_MACHINE_SDRAM
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default 0x0 if OR4_COLS_7
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default 0x400 if OR4_COLS_8
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default 0x800 if OR4_COLS_9
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default 0xc00 if OR4_COLS_10
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default 0x1000 if OR4_COLS_11
|
|
default 0x1400 if OR4_COLS_12
|
|
default 0x1800 if OR4_COLS_13
|
|
default 0x1c00 if OR4_COLS_14
|
|
|
|
config OR4_ROWS
|
|
hex
|
|
default 0x0 if !BR4_MACHINE_SDRAM
|
|
default 0x0 if OR4_ROWS_9
|
|
default 0x40 if OR4_ROWS_10
|
|
default 0x80 if OR4_ROWS_11
|
|
default 0xc0 if OR4_ROWS_12
|
|
default 0x100 if OR4_ROWS_13
|
|
default 0x140 if OR4_ROWS_14
|
|
default 0x180 if OR4_ROWS_15
|
|
|
|
config OR4_PMSEL
|
|
hex
|
|
default 0x0 if !BR4_MACHINE_SDRAM
|
|
default 0x0 if OR4_PMSEL_BTB
|
|
default 0x20 if OR4_PMSEL_KEPT_OPEN
|
|
|
|
config OR4_SCY
|
|
hex
|
|
default 0x0 if !BR4_MACHINE_GPCM && !BR4_MACHINE_FCM
|
|
default 0x0 if OR4_SCY_0
|
|
default 0x10 if OR4_SCY_1
|
|
default 0x20 if OR4_SCY_2
|
|
default 0x30 if OR4_SCY_3
|
|
default 0x40 if OR4_SCY_4
|
|
default 0x50 if OR4_SCY_5
|
|
default 0x60 if OR4_SCY_6
|
|
default 0x70 if OR4_SCY_7
|
|
default 0x80 if OR4_SCY_8
|
|
default 0x90 if OR4_SCY_9
|
|
default 0xa0 if OR4_SCY_10
|
|
default 0xb0 if OR4_SCY_11
|
|
default 0xc0 if OR4_SCY_12
|
|
default 0xd0 if OR4_SCY_13
|
|
default 0xe0 if OR4_SCY_14
|
|
default 0xf0 if OR4_SCY_15
|
|
|
|
config OR4_PGS
|
|
hex
|
|
default 0x0 if !BR4_MACHINE_FCM
|
|
default 0x0 if OR4_PGS_SMALL
|
|
default 0x400 if OR4_PGS_LARGE
|
|
|
|
config OR4_CSCT
|
|
hex
|
|
default 0x0 if !BR4_MACHINE_FCM
|
|
default 0x0 if OR4_CSCT_1_CYCLE
|
|
default 0x0 if OR4_CSCT_2_CYCLE
|
|
default 0x200 if OR4_CSCT_4_CYCLE
|
|
default 0x200 if OR4_CSCT_8_CYCLE
|
|
|
|
config OR4_CST
|
|
hex
|
|
default 0x0 if !BR4_MACHINE_FCM
|
|
default 0x0 if OR4_CST_COINCIDENT
|
|
default 0x100 if OR4_CST_QUARTER_CLOCK
|
|
default 0x0 if OR4_CST_HALF_CLOCK
|
|
default 0x100 if OR4_CST_ONE_CLOCK
|
|
|
|
config OR4_CHT
|
|
hex
|
|
default 0x0 if !BR4_MACHINE_FCM
|
|
default 0x0 if OR4_CHT_HALF_CLOCK
|
|
default 0x80 if OR4_CHT_ONE_CLOCK
|
|
default 0x0 if OR4_CHT_ONE_HALF_CLOCK
|
|
default 0x80 if OR4_CHT_TWO_CLOCK
|
|
|
|
config OR4_RST
|
|
hex
|
|
default 0x0 if !BR4_MACHINE_FCM
|
|
default 0x0 if OR4_RST_THREE_QUARTER_CLOCK
|
|
default 0x8 if OR4_RST_ONE_CLOCK
|
|
default 0x0 if OR4_RST_ONE_HALF_CLOCK
|
|
|
|
config OR4_CSNT
|
|
hex
|
|
default 0x0 if !BR4_MACHINE_GPCM
|
|
default 0x0 if OR4_CSNT_NORMAL
|
|
default 0x800 if OR4_CSNT_EARLIER
|
|
|
|
config OR4_ACS
|
|
hex
|
|
default 0x0 if !BR4_MACHINE_GPCM
|
|
default 0x0 if OR4_ACS_SAME_TIME
|
|
default 0x400 if OR4_ACS_QUARTER_CYCLE_EARLIER
|
|
default 0x600 if OR4_ACS_HALF_CYCLE_EARLIER
|
|
|
|
config OR4_XACS
|
|
hex
|
|
default 0x0 if !BR4_MACHINE_GPCM
|
|
default 0x0 if OR4_XACS_NORMAL
|
|
default 0x100 if OR4_XACS_EXTENDED
|
|
|
|
config OR4_SETA
|
|
hex
|
|
default 0x0 if !BR4_MACHINE_GPCM
|
|
default 0x0 if OR4_SETA_INTERNAL
|
|
default 0x8 if OR4_SETA_EXTERNAL
|
|
|
|
config OR4_TRLX
|
|
hex
|
|
default 0x0 if OR4_TRLX_NORMAL
|
|
default 0x4 if OR4_TRLX_RELAXED
|
|
|
|
config OR4_EHTR
|
|
hex
|
|
default 0x0 if OR4_EHTR_NORMAL
|
|
default 0x2 if OR4_EHTR_1_CYCLE
|
|
default 0x0 if OR4_EHTR_4_CYCLE
|
|
default 0x2 if OR4_EHTR_8_CYCLE
|
|
|
|
config OR4_EAD
|
|
hex
|
|
default 0x0 if ARCH_MPC8308
|
|
default 0x0 if OR4_EAD_NONE
|
|
default 0x1 if OR4_EAD_EXTRA
|