176 lines
3.9 KiB
ArmAsm
176 lines
3.9 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* On-chip UART initializaion for low-level debugging
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*
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* Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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*/
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#include <linux/serial_reg.h>
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#include <linux/linkage.h>
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#include "../bcu/bcu-regs.h"
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#include "../sc-regs.h"
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#include "../sg-regs.h"
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#if !defined(CONFIG_DEBUG_SEMIHOSTING)
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#include CONFIG_DEBUG_LL_INCLUDE
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#endif
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#define SG_REVISION_TYPE_SHIFT 16
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#define SG_REVISION_TYPE_MASK (0xff << SG_REVISION_TYPE_SHIFT)
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#define BAUDRATE 115200
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#define DIV_ROUND(x, d) (((x) + ((d) / 2)) / (d))
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.macro sg_set_pinsel, pin, muxval, mux_bits, reg_stride, ra, rd
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ldr \ra, =(SG_BASE + SG_PINCTRL_BASE + \pin * \mux_bits / 32 * \reg_stride)
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ldr \rd, [\ra]
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and \rd, \rd, #~(((1 << \mux_bits) - 1) << (\pin * \mux_bits % 32))
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orr \rd, \rd, #(\muxval << (\pin * \mux_bits % 32))
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str \rd, [\ra]
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.endm
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ENTRY(debug_ll_init)
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ldr r0, =(SG_BASE + SG_REVISION)
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ldr r1, [r0]
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and r1, r1, #SG_REVISION_TYPE_MASK
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mov r1, r1, lsr #SG_REVISION_TYPE_SHIFT
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#if defined(CONFIG_ARCH_UNIPHIER_LD4)
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#define UNIPHIER_LD4_UART_CLK 36864000
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cmp r1, #0x26
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bne ld4_end
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ldr r0, =(SG_BASE + SG_IECTRL)
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ldr r1, [r0]
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orr r1, r1, #1
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str r1, [r0]
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sg_set_pinsel 88, 1, 8, 4, r0, r1 @ HSDOUT6 -> TXD0
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ldr r3, =DIV_ROUND(UNIPHIER_LD4_UART_CLK, 16 * BAUDRATE)
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b init_uart
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ld4_end:
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER_PRO4)
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#define UNIPHIER_PRO4_UART_CLK 73728000
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cmp r1, #0x28
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bne pro4_end
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sg_set_pinsel 128, 0, 4, 8, r0, r1 @ TXD0 -> TXD0
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ldr r0, =(SG_BASE + SG_LOADPINCTRL)
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mov r1, #1
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str r1, [r0]
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ldr r0, =(SC_BASE + SC_CLKCTRL)
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ldr r1, [r0]
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orr r1, r1, #SC_CLKCTRL_CEN_PERI
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str r1, [r0]
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ldr r3, =DIV_ROUND(UNIPHIER_PRO4_UART_CLK, 16 * BAUDRATE)
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b init_uart
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pro4_end:
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER_SLD8)
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#define UNIPHIER_SLD8_UART_CLK 80000000
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cmp r1, #0x29
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bne sld8_end
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ldr r0, =(SG_BASE + SG_IECTRL)
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ldr r1, [r0]
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orr r1, r1, #1
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str r1, [r0]
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sg_set_pinsel 70, 3, 8, 4, r0, r1 @ HSDOUT0 -> TXD0
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ldr r3, =DIV_ROUND(UNIPHIER_SLD8_UART_CLK, 16 * BAUDRATE)
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b init_uart
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sld8_end:
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER_PRO5)
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#define UNIPHIER_PRO5_UART_CLK 73728000
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cmp r1, #0x2A
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bne pro5_end
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sg_set_pinsel 47, 0, 4, 8, r0, r1 @ TXD0 -> TXD0
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sg_set_pinsel 49, 0, 4, 8, r0, r1 @ TXD1 -> TXD1
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sg_set_pinsel 51, 0, 4, 8, r0, r1 @ TXD2 -> TXD2
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sg_set_pinsel 53, 0, 4, 8, r0, r1 @ TXD3 -> TXD3
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ldr r0, =(SG_BASE + SG_LOADPINCTRL)
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mov r1, #1
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str r1, [r0]
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ldr r0, =(SC_BASE + SC_CLKCTRL)
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ldr r1, [r0]
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orr r1, r1, #SC_CLKCTRL_CEN_PERI
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str r1, [r0]
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ldr r3, =DIV_ROUND(UNIPHIER_PRO5_UART_CLK, 16 * BAUDRATE)
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b init_uart
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pro5_end:
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER_PXS2)
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#define UNIPHIER_PXS2_UART_CLK 88900000
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cmp r1, #0x2E
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bne pxs2_end
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ldr r0, =(SG_BASE + SG_IECTRL)
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ldr r1, [r0]
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orr r1, r1, #1
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str r1, [r0]
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sg_set_pinsel 217, 8, 8, 4, r0, r1 @ TXD0 -> TXD0
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sg_set_pinsel 115, 8, 8, 4, r0, r1 @ TXD1 -> TXD1
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sg_set_pinsel 113, 8, 8, 4, r0, r1 @ TXD2 -> TXD2
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sg_set_pinsel 219, 8, 8, 4, r0, r1 @ TXD3 -> TXD3
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ldr r0, =(SC_BASE + SC_CLKCTRL)
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ldr r1, [r0]
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orr r1, r1, #SC_CLKCTRL_CEN_PERI
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str r1, [r0]
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ldr r3, =DIV_ROUND(UNIPHIER_PXS2_UART_CLK, 16 * BAUDRATE)
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b init_uart
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pxs2_end:
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER_LD6B)
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#define UNIPHIER_LD6B_UART_CLK 88900000
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cmp r1, #0x2F
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bne ld6b_end
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ldr r0, =(SG_BASE + SG_IECTRL)
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ldr r1, [r0]
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orr r1, r1, #1
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str r1, [r0]
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sg_set_pinsel 135, 3, 8, 4, r0, r1 @ PORT10 -> TXD0
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sg_set_pinsel 115, 0, 8, 4, r0, r1 @ TXD1 -> TXD1
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sg_set_pinsel 113, 2, 8, 4, r0, r1 @ SBO0 -> TXD2
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ldr r0, =(SC_BASE + SC_CLKCTRL)
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ldr r1, [r0]
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orr r1, r1, #SC_CLKCTRL_CEN_PERI
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str r1, [r0]
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ldr r3, =DIV_ROUND(UNIPHIER_LD6B_UART_CLK, 16 * BAUDRATE)
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b init_uart
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ld6b_end:
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#endif
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mov pc, lr
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init_uart:
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addruart r0, r1, r2
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mov r1, #UART_LCR_WLEN8 << 8
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str r1, [r0, #0x10]
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str r3, [r0, #0x24]
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mov pc, lr
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ENDPROC(debug_ll_init)
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