479 lines
15 KiB
C
479 lines
15 KiB
C
/*
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* linux/include/asm-arm/io.h
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*
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* Copyright (C) 1996-2000 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Modifications:
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* 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both
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* constant addresses and variable addresses.
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* 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture
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* specific IO header files.
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* 27-Mar-1999 PJB Second parameter of memcpy_toio is const..
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* 04-Apr-1999 PJB Added check_signature.
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* 12-Dec-1999 RMK More cleanups
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* 18-Jun-2000 RMK Removed virt_to_* and friends definitions
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*/
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#ifndef __ASM_ARM_IO_H
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#define __ASM_ARM_IO_H
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#ifdef __KERNEL__
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <asm/byteorder.h>
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#include <asm/memory.h>
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#include <asm/barriers.h>
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#if 0 /* XXX###XXX */
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#include <asm/arch/hardware.h>
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#endif /* XXX###XXX */
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static inline void sync(void)
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{
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}
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/*
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* Generic virtual read/write. Note that we don't support half-word
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* read/writes. We define __arch_*[bl] here, and leave __arch_*w
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* to the architecture specific code.
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*/
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#define __arch_getb(a) (*(volatile unsigned char *)(a))
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#define __arch_getw(a) (*(volatile unsigned short *)(a))
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#define __arch_getl(a) (*(volatile unsigned int *)(a))
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#define __arch_getq(a) (*(volatile unsigned long long *)(a))
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#define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v))
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#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v))
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#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v))
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#define __arch_putq(v,a) (*(volatile unsigned long long *)(a) = (v))
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static inline void __raw_writesb(unsigned long addr, const void *data,
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int bytelen)
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{
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uint8_t *buf = (uint8_t *)data;
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while(bytelen--)
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__arch_putb(*buf++, addr);
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}
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static inline void __raw_writesw(unsigned long addr, const void *data,
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int wordlen)
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{
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uint16_t *buf = (uint16_t *)data;
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while(wordlen--)
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__arch_putw(*buf++, addr);
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}
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static inline void __raw_writesl(unsigned long addr, const void *data,
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int longlen)
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{
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uint32_t *buf = (uint32_t *)data;
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while(longlen--)
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__arch_putl(*buf++, addr);
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}
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static inline void __raw_readsb(unsigned long addr, void *data, int bytelen)
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{
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uint8_t *buf = (uint8_t *)data;
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while(bytelen--)
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*buf++ = __arch_getb(addr);
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}
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static inline void __raw_readsw(unsigned long addr, void *data, int wordlen)
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{
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uint16_t *buf = (uint16_t *)data;
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while(wordlen--)
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*buf++ = __arch_getw(addr);
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}
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static inline void __raw_readsl(unsigned long addr, void *data, int longlen)
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{
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uint32_t *buf = (uint32_t *)data;
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while(longlen--)
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*buf++ = __arch_getl(addr);
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}
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#define __raw_writeb(v,a) __arch_putb(v,a)
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#define __raw_writew(v,a) __arch_putw(v,a)
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#define __raw_writel(v,a) __arch_putl(v,a)
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#define __raw_writeq(v,a) __arch_putq(v,a)
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#define __raw_readb(a) __arch_getb(a)
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#define __raw_readw(a) __arch_getw(a)
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#define __raw_readl(a) __arch_getl(a)
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#define __raw_readq(a) __arch_getq(a)
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/*
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* TODO: The kernel offers some more advanced versions of barriers, it might
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* have some advantages to use them instead of the simple one here.
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*/
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#define mb() dsb()
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#define __iormb() dmb()
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#define __iowmb() dmb()
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#define writeb(v,c) ({ u8 __v = v; __iowmb(); __arch_putb(__v,c); __v; })
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#define writew(v,c) ({ u16 __v = v; __iowmb(); __arch_putw(__v,c); __v; })
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#define writel(v,c) ({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v; })
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#define writeq(v,c) ({ u64 __v = v; __iowmb(); __arch_putq(__v,c); __v; })
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#define readb(c) ({ u8 __v = __arch_getb(c); __iormb(); __v; })
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#define readw(c) ({ u16 __v = __arch_getw(c); __iormb(); __v; })
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#define readl(c) ({ u32 __v = __arch_getl(c); __iormb(); __v; })
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#define readq(c) ({ u64 __v = __arch_getq(c); __iormb(); __v; })
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/*
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* Relaxed I/O memory access primitives. These follow the Device memory
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* ordering rules but do not guarantee any ordering relative to Normal memory
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* accesses.
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*/
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#define readb_relaxed(c) ({ u8 __r = __raw_readb(c); __r; })
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#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \
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__raw_readw(c)); __r; })
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#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \
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__raw_readl(c)); __r; })
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#define readq_relaxed(c) ({ u64 __r = le64_to_cpu((__force __le64) \
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__raw_readq(c)); __r; })
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#define writeb_relaxed(v, c) ((void)__raw_writeb((v), (c)))
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#define writew_relaxed(v, c) ((void)__raw_writew((__force u16) \
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cpu_to_le16(v), (c)))
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#define writel_relaxed(v, c) ((void)__raw_writel((__force u32) \
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cpu_to_le32(v), (c)))
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#define writeq_relaxed(v, c) ((void)__raw_writeq((__force u64) \
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cpu_to_le64(v), (c)))
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/*
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* The compiler seems to be incapable of optimising constants
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* properly. Spell it out to the compiler in some cases.
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* These are only valid for small values of "off" (< 1<<12)
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*/
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#define __raw_base_writeb(val,base,off) __arch_base_putb(val,base,off)
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#define __raw_base_writew(val,base,off) __arch_base_putw(val,base,off)
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#define __raw_base_writel(val,base,off) __arch_base_putl(val,base,off)
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#define __raw_base_readb(base,off) __arch_base_getb(base,off)
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#define __raw_base_readw(base,off) __arch_base_getw(base,off)
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#define __raw_base_readl(base,off) __arch_base_getl(base,off)
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/*
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* Clear and set bits in one shot. These macros can be used to clear and
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* set multiple bits in a register using a single call. These macros can
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* also be used to set a multiple-bit bit pattern using a mask, by
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* specifying the mask in the 'clear' parameter and the new bit pattern
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* in the 'set' parameter.
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*/
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#define out_arch(type,endian,a,v) __raw_write##type(cpu_to_##endian(v),a)
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#define in_arch(type,endian,a) endian##_to_cpu(__raw_read##type(a))
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#define out_le64(a,v) out_arch(q,le64,a,v)
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#define out_le32(a,v) out_arch(l,le32,a,v)
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#define out_le16(a,v) out_arch(w,le16,a,v)
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#define in_le64(a) in_arch(q,le64,a)
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#define in_le32(a) in_arch(l,le32,a)
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#define in_le16(a) in_arch(w,le16,a)
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#define out_be32(a,v) out_arch(l,be32,a,v)
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#define out_be16(a,v) out_arch(w,be16,a,v)
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#define in_be32(a) in_arch(l,be32,a)
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#define in_be16(a) in_arch(w,be16,a)
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#define out_32(a,v) __raw_writel(v,a)
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#define out_16(a,v) __raw_writew(v,a)
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#define out_8(a,v) __raw_writeb(v,a)
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#define in_32(a) __raw_readl(a)
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#define in_16(a) __raw_readw(a)
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#define in_8(a) __raw_readb(a)
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#define clrbits(type, addr, clear) \
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out_##type((addr), in_##type(addr) & ~(clear))
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#define setbits(type, addr, set) \
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out_##type((addr), in_##type(addr) | (set))
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#define clrsetbits(type, addr, clear, set) \
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out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
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#define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
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#define setbits_be32(addr, set) setbits(be32, addr, set)
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#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
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#define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
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#define setbits_le32(addr, set) setbits(le32, addr, set)
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#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
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#define clrbits_32(addr, clear) clrbits(32, addr, clear)
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#define setbits_32(addr, set) setbits(32, addr, set)
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#define clrsetbits_32(addr, clear, set) clrsetbits(32, addr, clear, set)
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#define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
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#define setbits_be16(addr, set) setbits(be16, addr, set)
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#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
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#define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
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#define setbits_le16(addr, set) setbits(le16, addr, set)
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#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
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#define clrbits_16(addr, clear) clrbits(16, addr, clear)
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#define setbits_16(addr, set) setbits(16, addr, set)
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#define clrsetbits_16(addr, clear, set) clrsetbits(16, addr, clear, set)
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#define clrbits_8(addr, clear) clrbits(8, addr, clear)
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#define setbits_8(addr, set) setbits(8, addr, set)
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#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
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/*
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* Now, pick up the machine-defined IO definitions
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*/
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#if 0 /* XXX###XXX */
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#include <asm/arch/io.h>
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#endif /* XXX###XXX */
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/*
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* IO port access primitives
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* -------------------------
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*
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* The ARM doesn't have special IO access instructions; all IO is memory
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* mapped. Note that these are defined to perform little endian accesses
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* only. Their primary purpose is to access PCI and ISA peripherals.
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*
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* Note that for a big endian machine, this implies that the following
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* big endian mode connectivity is in place, as described by numerous
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* ARM documents:
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*
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* PCI: D0-D7 D8-D15 D16-D23 D24-D31
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* ARM: D24-D31 D16-D23 D8-D15 D0-D7
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*
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* The machine specific io.h include defines __io to translate an "IO"
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* address to a memory address.
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*
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* Note that we prevent GCC re-ordering or caching values in expressions
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* by introducing sequence points into the in*() definitions. Note that
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* __raw_* do not guarantee this behaviour.
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*
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* The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
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*/
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#ifdef __io
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#define outb(v,p) __raw_writeb(v,__io(p))
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#define outw(v,p) __raw_writew(cpu_to_le16(v),__io(p))
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#define outl(v,p) __raw_writel(cpu_to_le32(v),__io(p))
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#define inb(p) ({ unsigned int __v = __raw_readb(__io(p)); __v; })
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#define inw(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; })
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#define inl(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; })
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#define outsb(p,d,l) __raw_writesb(__io(p),d,l)
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#define outsw(p,d,l) __raw_writesw(__io(p),d,l)
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#define outsl(p,d,l) __raw_writesl(__io(p),d,l)
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#define insb(p,d,l) __raw_readsb(__io(p),d,l)
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#define insw(p,d,l) __raw_readsw(__io(p),d,l)
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#define insl(p,d,l) __raw_readsl(__io(p),d,l)
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#endif
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#define outb_p(val,port) outb((val),(port))
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#define outw_p(val,port) outw((val),(port))
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#define outl_p(val,port) outl((val),(port))
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#define inb_p(port) inb((port))
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#define inw_p(port) inw((port))
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#define inl_p(port) inl((port))
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#define outsb_p(port,from,len) outsb(port,from,len)
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#define outsw_p(port,from,len) outsw(port,from,len)
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#define outsl_p(port,from,len) outsl(port,from,len)
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#define insb_p(port,to,len) insb(port,to,len)
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#define insw_p(port,to,len) insw(port,to,len)
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#define insl_p(port,to,len) insl(port,to,len)
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#define writesl(a, d, s) __raw_writesl((unsigned long)a, d, s)
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#define readsl(a, d, s) __raw_readsl((unsigned long)a, d, s)
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#define writesw(a, d, s) __raw_writesw((unsigned long)a, d, s)
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#define readsw(a, d, s) __raw_readsw((unsigned long)a, d, s)
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#define writesb(a, d, s) __raw_writesb((unsigned long)a, d, s)
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#define readsb(a, d, s) __raw_readsb((unsigned long)a, d, s)
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/*
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* DMA-consistent mapping functions. These allocate/free a region of
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* uncached, unwrite-buffered mapped memory space for use with DMA
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* devices. This is the "generic" version. The PCI specific version
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* is in pci.h
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*/
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extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle);
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extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle);
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extern void consistent_sync(void *vaddr, size_t size, int rw);
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/*
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* String version of IO memory access ops:
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*/
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extern void _memcpy_fromio(void *, unsigned long, size_t);
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extern void _memcpy_toio(unsigned long, const void *, size_t);
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extern void _memset_io(unsigned long, int, size_t);
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extern void __readwrite_bug(const char *fn);
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/* Optimized copy functions to read from/write to IO sapce */
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#ifdef CONFIG_ARM64
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/*
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* Copy data from IO memory space to "real" memory space.
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*/
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static inline
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void __memcpy_fromio(void *to, const volatile void __iomem *from, size_t count)
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{
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while (count && !IS_ALIGNED((unsigned long)from, 8)) {
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*(u8 *)to = __raw_readb(from);
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from++;
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to++;
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count--;
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}
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while (count >= 8) {
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*(u64 *)to = __raw_readq(from);
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from += 8;
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to += 8;
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count -= 8;
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}
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while (count) {
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*(u8 *)to = __raw_readb(from);
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from++;
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to++;
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count--;
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}
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}
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/*
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* Copy data from "real" memory space to IO memory space.
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*/
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static inline
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void __memcpy_toio(volatile void __iomem *to, const void *from, size_t count)
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{
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while (count && !IS_ALIGNED((unsigned long)to, 8)) {
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__raw_writeb(*(u8 *)from, to);
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from++;
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to++;
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count--;
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}
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while (count >= 8) {
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__raw_writeq(*(u64 *)from, to);
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from += 8;
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to += 8;
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count -= 8;
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}
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while (count) {
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__raw_writeb(*(u8 *)from, to);
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from++;
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to++;
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count--;
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}
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}
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/*
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* "memset" on IO memory space.
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*/
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static inline
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void __memset_io(volatile void __iomem *dst, int c, size_t count)
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{
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u64 qc = (u8)c;
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qc |= qc << 8;
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qc |= qc << 16;
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qc |= qc << 32;
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while (count && !IS_ALIGNED((unsigned long)dst, 8)) {
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__raw_writeb(c, dst);
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dst++;
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count--;
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}
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while (count >= 8) {
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__raw_writeq(qc, dst);
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dst += 8;
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count -= 8;
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}
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while (count) {
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__raw_writeb(c, dst);
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dst++;
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count--;
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}
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}
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#endif /* CONFIG_ARM64 */
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#ifdef CONFIG_ARM64
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#define memset_io(a, b, c) __memset_io((a), (b), (c))
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#define memcpy_fromio(a, b, c) __memcpy_fromio((a), (b), (c))
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#define memcpy_toio(a, b, c) __memcpy_toio((a), (b), (c))
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#else
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#define memset_io(a, b, c) memset((void *)(a), (b), (c))
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#define memcpy_fromio(a, b, c) memcpy((a), (void *)(b), (c))
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#define memcpy_toio(a, b, c) memcpy((void *)(a), (b), (c))
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#endif
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/*
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* If this architecture has ISA IO, then define the isa_read/isa_write
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* macros.
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*/
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#ifdef __mem_isa
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#define isa_readb(addr) __raw_readb(__mem_isa(addr))
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#define isa_readw(addr) __raw_readw(__mem_isa(addr))
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#define isa_readl(addr) __raw_readl(__mem_isa(addr))
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|
#define isa_writeb(val,addr) __raw_writeb(val,__mem_isa(addr))
|
|
#define isa_writew(val,addr) __raw_writew(val,__mem_isa(addr))
|
|
#define isa_writel(val,addr) __raw_writel(val,__mem_isa(addr))
|
|
#define isa_memset_io(a,b,c) _memset_io(__mem_isa(a),(b),(c))
|
|
#define isa_memcpy_fromio(a,b,c) _memcpy_fromio((a),__mem_isa(b),(c))
|
|
#define isa_memcpy_toio(a,b,c) _memcpy_toio(__mem_isa((a)),(b),(c))
|
|
|
|
#define isa_eth_io_copy_and_sum(a,b,c,d) \
|
|
eth_copy_and_sum((a),__mem_isa(b),(c),(d))
|
|
|
|
static inline int
|
|
isa_check_signature(unsigned long io_addr, const unsigned char *signature,
|
|
int length)
|
|
{
|
|
int retval = 0;
|
|
do {
|
|
if (isa_readb(io_addr) != *signature)
|
|
goto out;
|
|
io_addr++;
|
|
signature++;
|
|
length--;
|
|
} while (length);
|
|
retval = 1;
|
|
out:
|
|
return retval;
|
|
}
|
|
|
|
#else /* __mem_isa */
|
|
|
|
#define isa_readb(addr) (__readwrite_bug("isa_readb"),0)
|
|
#define isa_readw(addr) (__readwrite_bug("isa_readw"),0)
|
|
#define isa_readl(addr) (__readwrite_bug("isa_readl"),0)
|
|
#define isa_writeb(val,addr) __readwrite_bug("isa_writeb")
|
|
#define isa_writew(val,addr) __readwrite_bug("isa_writew")
|
|
#define isa_writel(val,addr) __readwrite_bug("isa_writel")
|
|
#define isa_memset_io(a,b,c) __readwrite_bug("isa_memset_io")
|
|
#define isa_memcpy_fromio(a,b,c) __readwrite_bug("isa_memcpy_fromio")
|
|
#define isa_memcpy_toio(a,b,c) __readwrite_bug("isa_memcpy_toio")
|
|
|
|
#define isa_eth_io_copy_and_sum(a,b,c,d) \
|
|
__readwrite_bug("isa_eth_io_copy_and_sum")
|
|
|
|
#define isa_check_signature(io,sig,len) (0)
|
|
|
|
#endif /* __mem_isa */
|
|
#endif /* __KERNEL__ */
|
|
|
|
#include <asm-generic/io.h>
|
|
#include <iotrace.h>
|
|
|
|
#endif /* __ASM_ARM_IO_H */
|