387 lines
8.8 KiB
C
387 lines
8.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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*
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* (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
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*/
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#ifndef __ASM_ARCH_MX35_H
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#define __ASM_ARCH_MX35_H
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#define ARCH_MXC
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/*
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* IRAM
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*/
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#define IRAM_BASE_ADDR 0x10000000 /* internal ram */
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#define IRAM_SIZE 0x00020000 /* 128 KB */
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#define LOW_LEVEL_SRAM_STACK 0x1001E000
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/*
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* AIPS 1
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*/
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#define AIPS1_BASE_ADDR 0x43F00000
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#define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR
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#define MAX_BASE_ADDR 0x43F04000
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#define EVTMON_BASE_ADDR 0x43F08000
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#define CLKCTL_BASE_ADDR 0x43F0C000
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#define I2C1_BASE_ADDR 0x43F80000
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#define I2C3_BASE_ADDR 0x43F84000
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#define ATA_BASE_ADDR 0x43F8C000
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#define UART1_BASE 0x43F90000
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#define UART2_BASE 0x43F94000
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#define I2C2_BASE_ADDR 0x43F98000
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#define CSPI1_BASE_ADDR 0x43FA4000
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#define IOMUXC_BASE_ADDR 0x43FAC000
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/*
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* SPBA
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*/
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#define SPBA_BASE_ADDR 0x50000000
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#define UART3_BASE 0x5000C000
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#define CSPI2_BASE_ADDR 0x50010000
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#define ATA_DMA_BASE_ADDR 0x50020000
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#define FEC_BASE_ADDR 0x50038000
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#define SPBA_CTRL_BASE_ADDR 0x5003C000
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/*
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* AIPS 2
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*/
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#define AIPS2_BASE_ADDR 0x53F00000
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#define AIPS2_CTRL_BASE_ADDR AIPS2_BASE_ADDR
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#define CCM_BASE_ADDR 0x53F80000
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#define GPT1_BASE_ADDR 0x53F90000
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#define EPIT1_BASE_ADDR 0x53F94000
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#define EPIT2_BASE_ADDR 0x53F98000
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#define GPIO3_BASE_ADDR 0x53FA4000
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#define MMC_SDHC1_BASE_ADDR 0x53FB4000
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#define MMC_SDHC2_BASE_ADDR 0x53FB8000
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#define MMC_SDHC3_BASE_ADDR 0x53FBC000
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#define IPU_CTRL_BASE_ADDR 0x53FC0000
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#define GPIO1_BASE_ADDR 0x53FCC000
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#define GPIO2_BASE_ADDR 0x53FD0000
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#define SDMA_BASE_ADDR 0x53FD4000
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#define RTC_BASE_ADDR 0x53FD8000
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#define WDOG1_BASE_ADDR 0x53FDC000
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#define PWM_BASE_ADDR 0x53FE0000
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#define RTIC_BASE_ADDR 0x53FEC000
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#define IIM_BASE_ADDR 0x53FF0000
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#define IMX_USB_BASE 0x53FF4000
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#define IMX_USB_PORT_OFFSET 0x400
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#define IMX_CCM_BASE CCM_BASE_ADDR
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/*
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* ROMPATCH and AVIC
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*/
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#define ROMPATCH_BASE_ADDR 0x60000000
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#define AVIC_BASE_ADDR 0x68000000
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/*
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* NAND, SDRAM, WEIM, M3IF, EMI controllers
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*/
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#define EXT_MEM_CTRL_BASE 0xB8000000
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#define ESDCTL_BASE_ADDR 0xB8001000
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#define WEIM_BASE_ADDR 0xB8002000
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#define WEIM_CTRL_CS0 WEIM_BASE_ADDR
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#define WEIM_CTRL_CS1 (WEIM_BASE_ADDR + 0x10)
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#define WEIM_CTRL_CS2 (WEIM_BASE_ADDR + 0x20)
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#define WEIM_CTRL_CS3 (WEIM_BASE_ADDR + 0x30)
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#define WEIM_CTRL_CS4 (WEIM_BASE_ADDR + 0x40)
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#define WEIM_CTRL_CS5 (WEIM_BASE_ADDR + 0x50)
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#define M3IF_BASE_ADDR 0xB8003000
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#define EMI_BASE_ADDR 0xB8004000
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#define NFC_BASE_ADDR 0xBB000000
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/*
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* Memory regions and CS
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*/
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#define IPU_MEM_BASE_ADDR 0x70000000
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#define CSD0_BASE_ADDR 0x80000000
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#define CSD1_BASE_ADDR 0x90000000
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#define CS0_BASE_ADDR 0xA0000000
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#define CS1_BASE_ADDR 0xA8000000
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#define CS2_BASE_ADDR 0xB0000000
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#define CS3_BASE_ADDR 0xB2000000
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#define CS4_BASE_ADDR 0xB4000000
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#define CS5_BASE_ADDR 0xB6000000
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/*
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* IRQ Controller Register Definitions.
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*/
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#define AVIC_NIMASK 0x04
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#define AVIC_INTTYPEH 0x18
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#define AVIC_INTTYPEL 0x1C
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/* L210 */
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#define L2CC_BASE_ADDR 0x30000000
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#define L2_CACHE_LINE_SIZE 32
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#define L2_CACHE_CTL_REG 0x100
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#define L2_CACHE_AUX_CTL_REG 0x104
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#define L2_CACHE_SYNC_REG 0x730
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#define L2_CACHE_INV_LINE_REG 0x770
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#define L2_CACHE_INV_WAY_REG 0x77C
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#define L2_CACHE_CLEAN_LINE_REG 0x7B0
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#define L2_CACHE_CLEAN_INV_LINE_REG 0x7F0
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#define L2_CACHE_DBG_CTL_REG 0xF40
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#define CLKMODE_AUTO 0
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#define CLKMODE_CONSUMER 1
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#define PLL_PD(x) (((x) & 0xf) << 26)
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#define PLL_MFD(x) (((x) & 0x3ff) << 16)
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#define PLL_MFI(x) (((x) & 0xf) << 10)
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#define PLL_MFN(x) (((x) & 0x3ff) << 0)
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#define _PLL_BRM(x) ((x) << 31)
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#define _PLL_PD(x) (((x) - 1) << 26)
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#define _PLL_MFD(x) (((x) - 1) << 16)
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#define _PLL_MFI(x) ((x) << 10)
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#define _PLL_MFN(x) (x)
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#define _PLL_SETTING(brm, pd, mfd, mfi, mfn) \
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(_PLL_BRM(brm) | _PLL_PD(pd) | _PLL_MFD(mfd) | _PLL_MFI(mfi) |\
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_PLL_MFN(mfn))
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#define CCM_MPLL_532_HZ _PLL_SETTING(1, 1, 12, 11, 1)
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#define CCM_MPLL_399_HZ _PLL_SETTING(0, 1, 16, 8, 5)
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#define CCM_PPLL_300_HZ _PLL_SETTING(0, 1, 4, 6, 1)
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#define CSCR_U(x) (WEIM_CTRL_CS#x + 0)
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#define CSCR_L(x) (WEIM_CTRL_CS#x + 4)
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#define CSCR_A(x) (WEIM_CTRL_CS#x + 8)
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#define IIM_SREV 0x24
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#define ROMPATCH_REV 0x40
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#define IPU_CONF IPU_CTRL_BASE_ADDR
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#define IPU_CONF_PXL_ENDIAN (1<<8)
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#define IPU_CONF_DU_EN (1<<7)
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#define IPU_CONF_DI_EN (1<<6)
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#define IPU_CONF_ADC_EN (1<<5)
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#define IPU_CONF_SDC_EN (1<<4)
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#define IPU_CONF_PF_EN (1<<3)
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#define IPU_CONF_ROT_EN (1<<2)
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#define IPU_CONF_IC_EN (1<<1)
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#define IPU_CONF_CSI_EN (1<<0)
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/*
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* CSPI register definitions
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*/
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#define MXC_CSPI
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#define MXC_CSPICTRL_EN (1 << 0)
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#define MXC_CSPICTRL_MODE (1 << 1)
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#define MXC_CSPICTRL_XCH (1 << 2)
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#define MXC_CSPICTRL_SMC (1 << 3)
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#define MXC_CSPICTRL_POL (1 << 4)
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#define MXC_CSPICTRL_PHA (1 << 5)
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#define MXC_CSPICTRL_SSCTL (1 << 6)
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#define MXC_CSPICTRL_SSPOL (1 << 7)
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#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
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#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
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#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)
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#define MXC_CSPICTRL_TC (1 << 7)
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#define MXC_CSPICTRL_RXOVF (1 << 6)
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#define MXC_CSPICTRL_MAXBITS 0xfff
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#define MXC_CSPIPERIOD_32KHZ (1 << 15)
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#define MAX_SPI_BYTES 4
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#define MXC_SPI_BASE_ADDRESSES \
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0x43fa4000, \
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0x50010000,
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#define GPIO_PORT_NUM 3
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#define GPIO_NUM_PIN 32
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#define CHIP_REV_1_0 0x10
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#define CHIP_REV_2_0 0x20
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#define BOARD_REV_1_0 0x0
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#define BOARD_REV_2_0 0x1
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#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
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#include <asm/types.h>
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/* Clock Control Module (CCM) registers */
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struct ccm_regs {
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u32 ccmr; /* Control */
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u32 pdr0; /* Post divider 0 */
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u32 pdr1; /* Post divider 1 */
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u32 pdr2; /* Post divider 2 */
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u32 pdr3; /* Post divider 3 */
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u32 pdr4; /* Post divider 4 */
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u32 rcsr; /* CCM Status */
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u32 mpctl; /* Core PLL Control */
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u32 ppctl; /* Peripheral PLL Control */
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u32 acmr; /* Audio clock mux */
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u32 cosr; /* Clock out source */
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u32 cgr0; /* Clock Gating Control 0 */
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u32 cgr1; /* Clock Gating Control 1 */
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u32 cgr2; /* Clock Gating Control 2 */
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u32 cgr3; /* Clock Gating Control 3 */
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u32 reserved;
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u32 dcvr0; /* DPTC Comparator 0 */
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u32 dcvr1; /* DPTC Comparator 0 */
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u32 dcvr2; /* DPTC Comparator 0 */
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u32 dcvr3; /* DPTC Comparator 0 */
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u32 ltr0; /* Load Tracking 0 */
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u32 ltr1; /* Load Tracking 1 */
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u32 ltr2; /* Load Tracking 2 */
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u32 ltr3; /* Load Tracking 3 */
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u32 ltbr0; /* Load Tracking Buffer 0 */
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};
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/* IIM control registers */
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struct iim_regs {
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u32 iim_stat;
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u32 iim_statm;
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u32 iim_err;
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u32 iim_emask;
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u32 iim_fctl;
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u32 iim_ua;
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u32 iim_la;
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u32 iim_sdat;
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u32 iim_prev;
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u32 iim_srev;
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u32 iim_prg_p;
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u32 iim_scs0;
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u32 iim_scs1;
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u32 iim_scs2;
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u32 iim_scs3;
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u32 res1[0x1f1];
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struct fuse_bank {
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u32 fuse_regs[0x20];
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u32 fuse_rsvd[0xe0];
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} bank[3];
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};
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struct fuse_bank0_regs {
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u32 fuse0_7[8];
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u32 uid[8];
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u32 fuse16_31[0x10];
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};
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struct fuse_bank1_regs {
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u32 fuse0_21[0x16];
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u32 usr;
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u32 fuse23_31[9];
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};
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/* General Purpose Timer (GPT) registers */
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struct gpt_regs {
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u32 ctrl; /* control */
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u32 pre; /* prescaler */
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u32 stat; /* status */
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u32 intr; /* interrupt */
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u32 cmp[3]; /* output compare 1-3 */
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u32 capt[2]; /* input capture 1-2 */
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u32 counter; /* counter */
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};
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/* CSPI registers */
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struct cspi_regs {
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u32 rxdata;
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u32 txdata;
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u32 ctrl;
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u32 intr;
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u32 dma;
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u32 stat;
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u32 period;
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u32 test;
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};
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struct esdc_regs {
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u32 esdctl0;
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u32 esdcfg0;
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u32 esdctl1;
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u32 esdcfg1;
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u32 esdmisc;
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u32 reserved[4];
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u32 esdcdly[5];
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u32 esdcdlyl;
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};
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#define ESDC_MISC_RST (1 << 1)
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#define ESDC_MISC_MDDR_EN (1 << 2)
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#define ESDC_MISC_MDDR_DL_RST (1 << 3)
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#define ESDC_MISC_DDR_EN (1 << 8)
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#define ESDC_MISC_DDR2_EN (1 << 9)
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/* Multi-Layer AHB Crossbar Switch (MAX) registers */
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struct max_regs {
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u32 mpr0;
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u32 pad00[3];
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u32 sgpcr0;
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u32 pad01[59];
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u32 mpr1;
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u32 pad02[3];
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u32 sgpcr1;
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u32 pad03[59];
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u32 mpr2;
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u32 pad04[3];
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u32 sgpcr2;
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u32 pad05[59];
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u32 mpr3;
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u32 pad06[3];
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u32 sgpcr3;
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u32 pad07[59];
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u32 mpr4;
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u32 pad08[3];
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u32 sgpcr4;
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u32 pad09[251];
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u32 mgpcr0;
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u32 pad10[63];
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u32 mgpcr1;
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u32 pad11[63];
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u32 mgpcr2;
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u32 pad12[63];
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u32 mgpcr3;
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u32 pad13[63];
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u32 mgpcr4;
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u32 pad14[63];
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u32 mgpcr5;
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};
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/* AHB <-> IP-Bus Interface (AIPS) */
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struct aips_regs {
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u32 mpr_0_7;
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u32 mpr_8_15;
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u32 pad0[6];
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u32 pacr_0_7;
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u32 pacr_8_15;
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u32 pacr_16_23;
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u32 pacr_24_31;
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u32 pad1[4];
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u32 opacr_0_7;
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u32 opacr_8_15;
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u32 opacr_16_23;
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u32 opacr_24_31;
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u32 opacr_32_39;
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};
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/*
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* NFMS bit in RCSR register for pagesize of nandflash
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*/
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#define NFMS_BIT 8
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#define NFMS_NF_DWIDTH 14
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#define NFMS_NF_PG_SZ 8
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#define CCM_RCSR_NF_16BIT_SEL (1 << 14)
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#endif
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/*
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* Generic timer support
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*/
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#ifdef CONFIG_MX35_CLK32
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#define CONFIG_SYS_TIMER_RATE CONFIG_MX35_CLK32
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#else
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#define CONFIG_SYS_TIMER_RATE 32768
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#endif
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#define CONFIG_SYS_TIMER_COUNTER (GPT1_BASE_ADDR+36)
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#endif /* __ASM_ARCH_MX35_H */
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