64 lines
2.1 KiB
C
64 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2017 NXP Semiconductor, Inc.
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*
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*/
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#ifndef __FSL_STREAM_ID_H
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#define __FSL_STREAM_ID_H
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/*
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* Stream IDs on Chassis-2 (for example ls1043a, ls1046a, ls1012) devices
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* are not hardwired and are programmed by sw. There are a limited number
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* of stream IDs available, and the partitioning of them is scenario
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* dependent. This header defines the partitioning between legacy, PCI,
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* and DPAA1 devices.
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*
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* This partitioning can be customized in this file depending
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* on the specific hardware config:
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*
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* -non-PCI legacy, platform devices (USB, SDHC, SATA, DMA, QE etc)
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* -all legacy devices get a unique stream ID assigned and programmed in
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* their AMQR registers by u-boot
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*
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* -PCIe
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* -there is a range of stream IDs set aside for PCI in this
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* file. U-boot will scan the PCI bus and for each device discovered:
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* -allocate a streamID
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* -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID'
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* -set a msi-map entry in the PEXn controller node in the
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* device tree (see Documentation/devicetree/bindings/pci/pci-msi.txt
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* for more info on the msi-map definition)
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* -set a iommu-map entry in the PEXn controller node in the
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* device tree (see Documentation/devicetree/bindings/pci/pci-iommu.txt
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* for more info on the iommu-map definition)
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*
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* -DPAA1
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* - Stream ids for DPAA1 use are reserved for future usecase.
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*
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*/
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#define FSL_INVALID_STREAM_ID 0
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/* legacy devices */
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#define FSL_USB1_STREAM_ID 1
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#define FSL_USB2_STREAM_ID 2
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#define FSL_USB3_STREAM_ID 3
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#define FSL_SDHC_STREAM_ID 4
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#define FSL_SATA_STREAM_ID 5
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#define FSL_QE_STREAM_ID 6
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#define FSL_QDMA_STREAM_ID 7
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#define FSL_EDMA_STREAM_ID 8
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#define FSL_ETR_STREAM_ID 9
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#define FSL_DEBUG_STREAM_ID 10
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/* PCI - programmed in PEXn_LUT */
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#define FSL_PEX_STREAM_ID_START 11
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#define FSL_PEX_STREAM_ID_END 26
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/* DPAA1 - Stream-ID that can be programmed in DPAA1 h/w */
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#define FSL_DPAA1_STREAM_ID_START 27
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#define FSL_DPAA1_STREAM_ID_END 63
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#endif
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