37 lines
1.1 KiB
C
37 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2013 Broadcom Corporation.
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*/
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#ifndef __ARCH_BCM281XX_SYSMAP_H
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#define BSC1_BASE_ADDR 0x3e016000
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#define BSC2_BASE_ADDR 0x3e017000
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#define BSC3_BASE_ADDR 0x3e018000
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#define DWDMA_AHB_BASE_ADDR 0x38100000
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#define ESUB_CLK_BASE_ADDR 0x38000000
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#define ESW_CONTRL_BASE_ADDR 0x38200000
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#define GPIO2_BASE_ADDR 0x35003000
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#define HSOTG_BASE_ADDR 0x3f120000
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#define HSOTG_CTRL_BASE_ADDR 0x3f130000
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#define KONA_MST_CLK_BASE_ADDR 0x3f001000
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#define KONA_SLV_CLK_BASE_ADDR 0x3e011000
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#define PMU_BSC_BASE_ADDR 0x3500d000
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#define PWRMGR_BASE_ADDR 0x35010000
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#define SDIO1_BASE_ADDR 0x3f180000
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#define SDIO2_BASE_ADDR 0x3f190000
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#define SDIO3_BASE_ADDR 0x3f1a0000
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#define SDIO4_BASE_ADDR 0x3f1b0000
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#define SECWD_BASE_ADDR 0x3500c000
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#define SECWD2_BASE_ADDR 0x35002f40
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#define TIMER_BASE_ADDR 0x3e00d000
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#define HSOTG_DCTL_OFFSET 0x00000804
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#define HSOTG_DCTL_SFTDISCON_MASK 0x00000002
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#define HSOTG_CTRL_PHY_P1CTL_OFFSET 0x00000008
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#define HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK 0x00000002
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#define HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK 0x00000001
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#endif
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