207 lines
3.2 KiB
Plaintext
207 lines
3.2 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* dts file for Xilinx ZynqMP zc1751-xm015-dc1
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*
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* (C) Copyright 2015 - 2018, Xilinx, Inc.
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*
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* Michal Simek <michal.simek@xilinx.com>
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*/
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/dts-v1/;
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#include "zynqmp.dtsi"
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#include "zynqmp-clk-ccf.dtsi"
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/ {
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model = "ZynqMP zc1751-xm015-dc1 RevA";
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compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
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aliases {
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ethernet0 = &gem3;
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gpio0 = &gpio;
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i2c0 = &i2c1;
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mmc0 = &sdhci0;
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mmc1 = &sdhci1;
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rtc0 = &rtc;
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serial0 = &uart0;
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spi0 = &qspi;
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usb0 = &usb0;
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};
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chosen {
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bootargs = "earlycon";
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stdout-path = "serial0:115200n8";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
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};
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};
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&fpd_dma_chan1 {
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status = "okay";
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};
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&fpd_dma_chan2 {
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status = "okay";
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};
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&fpd_dma_chan3 {
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status = "okay";
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};
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&fpd_dma_chan4 {
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status = "okay";
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};
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&fpd_dma_chan5 {
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status = "okay";
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};
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&fpd_dma_chan6 {
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status = "okay";
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};
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&fpd_dma_chan7 {
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status = "okay";
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};
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&fpd_dma_chan8 {
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status = "okay";
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};
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&gem3 {
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status = "okay";
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phy-handle = <&phy0>;
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phy-mode = "rgmii-id";
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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};
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&gpio {
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status = "okay";
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};
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&gpu {
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status = "okay";
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};
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&i2c1 {
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status = "okay";
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clock-frequency = <400000>;
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eeprom: eeprom@55 {
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compatible = "atmel,24c64"; /* 24AA64 */
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reg = <0x55>;
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};
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};
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&qspi {
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status = "okay";
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flash@0 {
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compatible = "m25p80", "jedec,spi-nor"; /* Micron MT25QU512ABB8ESF */
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x0>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <4>;
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spi-max-frequency = <108000000>; /* Based on DC1 spec */
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partition@qspi-fsbl-uboot { /* for testing purpose */
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label = "qspi-fsbl-uboot";
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reg = <0x0 0x100000>;
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};
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partition@qspi-linux { /* for testing purpose */
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label = "qspi-linux";
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reg = <0x100000 0x500000>;
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};
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partition@qspi-device-tree { /* for testing purpose */
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label = "qspi-device-tree";
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reg = <0x600000 0x20000>;
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};
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partition@qspi-rootfs { /* for testing purpose */
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label = "qspi-rootfs";
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reg = <0x620000 0x5E0000>;
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};
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};
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};
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&rtc {
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status = "okay";
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};
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&sata {
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status = "okay";
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/* SATA phy OOB timing settings */
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ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
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ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
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ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
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ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
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ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
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ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
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ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
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ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
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};
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/* eMMC */
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&sdhci0 {
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status = "okay";
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bus-width = <8>;
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xlnx,mio_bank = <0>;
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};
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/* SD1 with level shifter */
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&sdhci1 {
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status = "okay";
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no-1-8-v; /* for 1.0 silicon */
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xlnx,mio_bank = <1>;
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};
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&uart0 {
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status = "okay";
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};
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/* ULPI SMSC USB3320 */
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&usb0 {
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status = "okay";
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};
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&dwc3_0 {
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status = "okay";
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dr_mode = "host";
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};
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&xilinx_drm {
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status = "okay";
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};
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&xlnx_dp {
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status = "okay";
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};
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&xlnx_dp_sub {
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status = "okay";
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xlnx,vid-clk-pl;
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};
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&xlnx_dp_snd_pcm0 {
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status = "okay";
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};
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&xlnx_dp_snd_pcm1 {
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status = "okay";
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};
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&xlnx_dp_snd_card {
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status = "okay";
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};
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&xlnx_dp_snd_codec0 {
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status = "okay";
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};
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&xlnx_dpdma {
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status = "okay";
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};
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