497 lines
12 KiB
Plaintext
497 lines
12 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* dts file for Xilinx Versal a2197 RevA System Controller
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*
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* (C) Copyright 2019, Xilinx, Inc.
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*
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* Michal Simek <michal.simek@xilinx.com>
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*/
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/dts-v1/;
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#include "zynqmp.dtsi"
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#include "zynqmp-clk-ccf.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "Versal System Controller on a2197 Memory Char board RevA";
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compatible = "xlnx,zynqmp-m-a2197-02-revA", "xlnx,zynqmp-a2197-revA",
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"xlnx,zynqmp-a2197", "xlnx,zynqmp";
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aliases {
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ethernet0 = &gem0;
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gpio0 = &gpio;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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mmc0 = &sdhci0;
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mmc1 = &sdhci1;
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rtc0 = &rtc;
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &dcc;
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usb0 = &usb0;
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usb1 = &usb1;
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spi0 = &qspi;
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};
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chosen {
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bootargs = "earlycon";
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stdout-path = "serial0:115200n8";
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xlnx,eeprom = <&eeprom>;
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>; /* FIXME don't know how big memory is there */
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};
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ina226-vcc-aux {
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compatible = "iio-hwmon";
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io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>;
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};
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ina226-vcc-ram {
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compatible = "iio-hwmon";
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io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;
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};
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ina226-vcc1v1-lp4 {
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compatible = "iio-hwmon";
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io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;
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};
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ina226-vcc1v2-lp4 {
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compatible = "iio-hwmon";
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io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>;
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};
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ina226-vdd1-1v8-lp4 {
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compatible = "iio-hwmon";
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io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>;
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};
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};
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&qspi {
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status = "okay";
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is-dual = <1>;
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flash@0 {
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compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x0>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <4>;
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spi-max-frequency = <108000000>;
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};
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};
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&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */
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status = "okay";
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non-removable;
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disable-wp;
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bus-width = <8>;
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xlnx,mio_bank = <0>; /* FIXME tap delay */
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};
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&uart0 { /* uart0 MIO38-39 */
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status = "okay";
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u-boot,dm-pre-reloc;
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};
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&uart1 { /* uart1 MIO40-41 */
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status = "okay";
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u-boot,dm-pre-reloc;
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};
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&sdhci1 { /* sd1 MIO45-51 cd in place */
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status = "disable";
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no-1-8-v;
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disable-wp;
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xlnx,mio_bank = <1>;
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};
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&gem0 {
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status = "okay";
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phy-handle = <&phy0>;
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phy-mode = "sgmii";
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phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;
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phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */
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reg = <0>;
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};
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};
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&gpio {
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status = "okay";
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gpio-line-names = "SCLK_OUT", "MISO_MO1", "MO2", "MO3", "MOSI_MIO0", /* 0 - 4 */
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"N_SS_OUT", "", "SYS_CTRL0", "SYS_CTRL1", "SYS_CTRL2", /* 5 - 9 */
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"SYS_CTRL3", "SYS_CTRL4", "SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
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"EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
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"EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */
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"", "RXD0_IN", "TXD0_OUT", "TXD1_OUT", "RXD1_IN", /* 25 - 29 */
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"", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
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"LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
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"UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */
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"SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */
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"SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */
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"USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */
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"USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */
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"USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */
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"USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */
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"USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
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"", "", "", "", "", /* 78 - 79 */
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"", "", "", "", "", /* 80 - 84 */
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"", "", "", "", "", /* 85 -89 */
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"", "", "", "", "", /* 90 - 94 */
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"", "", "", "", "", /* 95 - 99 */
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"", "", "", "", "", /* 100 - 104 */
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"", "", "", "", "", /* 105 - 109 */
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"", "", "", "", "", /* 110 - 114 */
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"", "", "", "", "", /* 115 - 119 */
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"", "", "", "", "", /* 120 - 124 */
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"", "", "", "", "", /* 125 - 129 */
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"", "", "", "", "", /* 130 - 134 */
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"", "", "", "", "", /* 135 - 139 */
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"", "", "", "", "", /* 140 - 144 */
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"", "", "", "", "", /* 145 - 149 */
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"", "", "", "", "", /* 150 - 154 */
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"", "", "", "", "", /* 155 - 159 */
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"", "", "", "", "", /* 160 - 164 */
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"", "", "", "", "", /* 165 - 169 */
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"", "", "", ""; /* 170 - 174 */
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};
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&i2c0 { /* MIO 34-35 - can't stay here */
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status = "okay";
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clock-frequency = <400000>;
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i2c-mux@74 { /* u46 */
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compatible = "nxp,pca9548";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x74>;
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/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */
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i2c@0 { /* PMBUS must be enabled via SW21 */
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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reg_vcc1v2_lp4: tps544@15 { /* u97 */
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compatible = "ti,tps544b25";
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reg = <0x15>;
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};
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reg_vcc1v1_lp4: tps544@16 { /* u95 */
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compatible = "ti,tps544b25";
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reg = <0x16>;
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};
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reg_vdd1_1v8_lp4: tps544@17 { /* u99 */
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compatible = "ti,tps544b25";
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reg = <0x17>;
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};
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/* UTIL_PMBUS connection */
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reg_vcc1v8: tps544@13 { /* u92 */
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compatible = "ti,tps544b25";
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reg = <0x13>;
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};
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reg_vcc3v3: tps544@14 { /* u93 */
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compatible = "ti,tps544b25";
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reg = <0x14>;
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};
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reg_vcc5v0: tps544@1e { /* u94 */
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compatible = "ti,tps544b25";
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reg = <0x1e>;
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};
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reg_vpp_2v5_ddr4: tps544@1x { /* u3007 */
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compatible = "ti,tps544b25";
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reg = <0x17>; /* FIXME wrong in schematics */
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};
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};
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i2c@1 { /* PMBUS_INA226 */
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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vcc_aux: ina226@42 { /* u86 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-vcc-aux";
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reg = <0x42>;
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shunt-resistor = <5000>;
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};
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vcc_ram: ina226@43 { /* u81 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-vcc-ram";
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reg = <0x43>;
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shunt-resistor = <5000>;
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};
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vcc1v1_lp4: ina226@46 { /* u96 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-vcc1v1-lp4";
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reg = <0x46>;
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shunt-resistor = <5000>;
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};
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vcc1v2_lp4: ina226@47 { /* u98 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-vcc1v2-lp4";
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reg = <0x47>;
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shunt-resistor = <5000>;
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};
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vdd1_1v8_lp4: ina226@48 { /* u100 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-vdd1-1v8-lp4";
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reg = <0x48>;
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shunt-resistor = <5000>;
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};
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};
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i2c@2 { /* PMBUS1 */
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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reg_vccint: tps53681@c0 { /* u69 */
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compatible = "ti,tps53681", "ti,tps53679";
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reg = <0xc0>;
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};
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reg_vcc_pmc: tps544@7 { /* u80 */
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compatible = "ti,tps544b25";
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reg = <0x7>;
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};
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reg_vcc_ram: tps544@8 { /* u82 */
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compatible = "ti,tps544b25";
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reg = <0x8>;
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};
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reg_vcc_pslp: tps544@9 { /* u83 */
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compatible = "ti,tps544b25";
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reg = <0x9>;
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};
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reg_vcc_psfp: tps544@a { /* u84 */
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compatible = "ti,tps544b25";
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reg = <0xa>;
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};
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reg_vccaux: tps544@d { /* u85 */
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compatible = "ti,tps544b25";
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reg = <0xd>;
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};
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reg_vccaux_pmc: tps544@e { /* u87 */
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compatible = "ti,tps544b25";
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reg = <0xe>;
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};
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reg_vcco_500: tps544@f { /* u88 */
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compatible = "ti,tps544b25";
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reg = <0xf>;
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};
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reg_vcco_501: tps544@10 { /* u89 */
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compatible = "ti,tps544b25";
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reg = <0x10>;
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};
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reg_vcco_502: tps544@11 { /* u90 */
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compatible = "ti,tps544b25";
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reg = <0x11>;
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};
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reg_vcco_503: tps544@12 { /* u91 */
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compatible = "ti,tps544b25";
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reg = <0x12>;
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};
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};
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i2c@3 { /* MEM PMBUS - FIXME bug in schematics */
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#address-cells = <1>;
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#size-cells = <0>;
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/* reg = <3>; */
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};
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i2c@4 { /* LP_I2C_SM */
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <4>;
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/* connected to U20G */
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};
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i2c@5 { /* C0_DDR4_RDIMM */
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <5>;
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};
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i2c@6 { /* C2_DDR5_RDIMM */
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <6>;
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};
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i2c@7 { /* C3_DDR4_UDIMM */
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <7>;
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};
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};
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};
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/* TODO sysctrl via J239 */
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/* TODO samtec J212G/H via J242 */
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/* TODO teensy via U30 PCA9543A bus 1 */
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&i2c1 { /* i2c1 MIO 36-37 */
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status = "okay";
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clock-frequency = <400000>;
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/* Must be enabled via J242 */
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eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */
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compatible = "atmel,24c02";
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reg = <0x51>;
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};
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i2c-mux@74 { /* u47 */
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compatible = "nxp,pca9548";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x74>;
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/* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */
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dc_i2c: i2c@0 { /* DC_I2C */
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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/* Use for storing information about SC board */
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eeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */
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compatible = "atmel,24c08";
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reg = <0x54>;
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};
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si570_ref_clk: clock-generator@5d { /* u26 */
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#clock-cells = <0>;
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compatible = "silabs,si570";
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reg = <0x5d>; /* FIXME addr */
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temperature-stability = <50>;
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factory-fout = <156250000>; /* FIXME every chip can be different */
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clock-frequency = <33333333>;
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clock-output-names = "REF_CLK"; /* FIXME */
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};
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/* Connection via Samtec U20D */
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/* Use for storing information about X-PRC card */
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x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */
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compatible = "atmel,24c02";
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reg = <0x52>;
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};
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/* Use for setting up certain features on X-PRC card */
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x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */
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compatible = "nxp,pca9534";
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reg = <0x22>;
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gpio-controller; /* IRQ not connected */
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#gpio-cells = <2>;
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gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
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"", "", "", "";
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gtr_sel0 {
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gpio-hog;
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gpios = <0 0>;
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input; /* FIXME add meaning */
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line-name = "sw4_1";
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};
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gtr_sel1 {
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gpio-hog;
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gpios = <1 0>;
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input; /* FIXME add meaning */
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line-name = "sw4_2";
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};
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gtr_sel2 {
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gpio-hog;
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gpios = <2 0>;
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input; /* FIXME add meaning */
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line-name = "sw4_3";
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};
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gtr_sel3 {
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gpio-hog;
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gpios = <3 0>;
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input; /* FIXME add meaning */
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line-name = "sw4_4";
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};
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};
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};
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i2c@2 { /* C0_DDR4 */
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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si570_c0_ddr4: clock-generator@55 { /* u4 */
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#clock-cells = <0>;
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compatible = "silabs,si570";
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reg = <0x55>;
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temperature-stability = <50>;
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factory-fout = <30000000>;
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clock-frequency = <30000000>;
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clock-output-names = "C0_DD4_SI570_CLK";
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};
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};
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i2c@3 { /* C1_RLD3 */
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <3>;
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si570_c1_lp4: clock-generator@55 { /* u7 */
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#clock-cells = <0>;
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compatible = "silabs,si570";
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reg = <0x55>;
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temperature-stability = <50>;
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factory-fout = <30000000>;
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clock-frequency = <30000000>;
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clock-output-names = "C1_RLD3_SI570_CLK";
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};
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};
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i2c@4 { /* C2_DDR5 */
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <4>;
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si570_c2_lp4: clock-generator@55 { /* u10 */
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#clock-cells = <0>;
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compatible = "silabs,si570";
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reg = <0x55>;
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temperature-stability = <50>;
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factory-fout = <30000000>;
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clock-frequency = <30000000>;
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clock-output-names = "C2_DDR5_SI570_CLK";
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};
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};
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i2c@5 { /* C3_DDR4 */
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <5>;
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si570_c3_lp4: clock-generator@55 { /* u15 */
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#clock-cells = <0>;
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compatible = "silabs,si570";
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reg = <0x55>;
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temperature-stability = <50>;
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factory-fout = <30000000>;
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clock-frequency = <30000000>;
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clock-output-names = "C3_LP4_SI570_CLK";
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};
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};
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i2c@6 { /* HSDP_SI570 */
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <6>;
|
|
si570_hsdp: clock-generator@5d { /* u19 */
|
|
#clock-cells = <0>;
|
|
compatible = "silabs,si570";
|
|
reg = <0x5d>;
|
|
temperature-stability = <50>;
|
|
factory-fout = <156250000>;
|
|
clock-frequency = <156250000>;
|
|
clock-output-names = "HSDP_SI570";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&usb0 {
|
|
status = "okay";
|
|
xlnx,usb-polarity = <0>;
|
|
xlnx,usb-reset-mode = <0>;
|
|
};
|
|
|
|
&dwc3_0 {
|
|
status = "okay";
|
|
dr_mode = "host";
|
|
/* dr_mode = "peripheral"; */
|
|
maximum-speed = "high-speed";
|
|
};
|
|
|
|
&usb1 {
|
|
status = "disabled"; /* not at mem board */
|
|
xlnx,usb-polarity = <0>;
|
|
xlnx,usb-reset-mode = <0>;
|
|
};
|
|
|
|
&dwc3_1 {
|
|
/delete-property/ phy-names ;
|
|
/delete-property/ phys ;
|
|
maximum-speed = "high-speed";
|
|
snps,dis_u2_susphy_quirk ;
|
|
snps,dis_u3_susphy_quirk ;
|
|
status = "disabled";
|
|
};
|