697 lines
17 KiB
Plaintext
697 lines
17 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ or MIT)
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/*
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* Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/sun50i-h6-ccu.h>
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#include <dt-bindings/clock/sun50i-h6-r-ccu.h>
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#include <dt-bindings/clock/sun8i-de2.h>
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#include <dt-bindings/clock/sun8i-tcon-top.h>
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#include <dt-bindings/reset/sun50i-h6-ccu.h>
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#include <dt-bindings/reset/sun50i-h6-r-ccu.h>
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#include <dt-bindings/reset/sun8i-de2.h>
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/ {
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <0>;
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enable-method = "psci";
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};
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cpu1: cpu@1 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <1>;
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enable-method = "psci";
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};
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cpu2: cpu@2 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <2>;
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enable-method = "psci";
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};
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cpu3: cpu@3 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <3>;
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enable-method = "psci";
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};
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};
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de: display-engine {
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compatible = "allwinner,sun50i-h6-display-engine";
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allwinner,pipelines = <&mixer0>;
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status = "disabled";
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};
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iosc: internal-osc-clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <16000000>;
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clock-accuracy = <300000000>;
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clock-output-names = "iosc";
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};
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osc24M: osc24M_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "osc24M";
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};
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osc32k: osc32k_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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clock-output-names = "osc32k";
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 11
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 10
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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bus@1000000 {
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compatible = "allwinner,sun50i-h6-de3",
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"allwinner,sun50i-a64-de2";
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reg = <0x1000000 0x400000>;
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allwinner,sram = <&de2_sram 1>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x1000000 0x400000>;
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display_clocks: clock@0 {
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compatible = "allwinner,sun50i-h6-de3-clk";
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reg = <0x0 0x10000>;
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clocks = <&ccu CLK_DE>,
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<&ccu CLK_BUS_DE>;
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clock-names = "mod",
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"bus";
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resets = <&ccu RST_BUS_DE>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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mixer0: mixer@100000 {
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compatible = "allwinner,sun50i-h6-de3-mixer-0";
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reg = <0x100000 0x100000>;
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clocks = <&display_clocks CLK_BUS_MIXER0>,
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<&display_clocks CLK_MIXER0>;
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clock-names = "bus",
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"mod";
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resets = <&display_clocks RST_MIXER0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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mixer0_out: port@1 {
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reg = <1>;
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mixer0_out_tcon_top_mixer0: endpoint {
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remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
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};
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};
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};
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};
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};
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video-codec@1c0e000 {
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compatible = "allwinner,sun50i-h6-video-engine";
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reg = <0x01c0e000 0x2000>;
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clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
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<&ccu CLK_MBUS_VE>;
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clock-names = "ahb", "mod", "ram";
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resets = <&ccu RST_BUS_VE>;
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interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
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allwinner,sram = <&ve_sram 1>;
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};
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syscon: syscon@3000000 {
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compatible = "allwinner,sun50i-h6-system-control",
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"allwinner,sun50i-a64-system-control";
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reg = <0x03000000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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sram_c: sram@28000 {
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compatible = "mmio-sram";
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reg = <0x00028000 0x1e000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x00028000 0x1e000>;
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de2_sram: sram-section@0 {
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compatible = "allwinner,sun50i-h6-sram-c",
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"allwinner,sun50i-a64-sram-c";
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reg = <0x0000 0x1e000>;
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};
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};
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sram_c1: sram@1a00000 {
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compatible = "mmio-sram";
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reg = <0x01a00000 0x200000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x01a00000 0x200000>;
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ve_sram: sram-section@0 {
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compatible = "allwinner,sun50i-h6-sram-c1",
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"allwinner,sun4i-a10-sram-c1";
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reg = <0x000000 0x200000>;
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};
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};
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};
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ccu: clock@3001000 {
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compatible = "allwinner,sun50i-h6-ccu";
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reg = <0x03001000 0x1000>;
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clocks = <&osc24M>, <&osc32k>, <&iosc>;
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clock-names = "hosc", "losc", "iosc";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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dma: dma-controller@3002000 {
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compatible = "allwinner,sun50i-h6-dma";
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reg = <0x03002000 0x1000>;
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interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
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clock-names = "bus", "mbus";
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dma-channels = <16>;
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dma-requests = <46>;
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resets = <&ccu RST_BUS_DMA>;
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#dma-cells = <1>;
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};
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sid: sid@3006000 {
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compatible = "allwinner,sun50i-h6-sid";
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reg = <0x03006000 0x400>;
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};
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watchdog: watchdog@30090a0 {
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compatible = "allwinner,sun50i-h6-wdt",
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"allwinner,sun6i-a31-wdt";
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reg = <0x030090a0 0x20>;
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interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
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/* Broken on some H6 boards */
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status = "disabled";
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};
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pio: pinctrl@300b000 {
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compatible = "allwinner,sun50i-h6-pinctrl";
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reg = <0x0300b000 0x400>;
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interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_APB1>, <&osc24M>, <&osc32k>;
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clock-names = "apb", "hosc", "losc";
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gpio-controller;
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#gpio-cells = <3>;
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interrupt-controller;
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#interrupt-cells = <3>;
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ext_rgmii_pins: rgmii-pins {
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pins = "PD0", "PD1", "PD2", "PD3", "PD4",
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"PD5", "PD7", "PD8", "PD9", "PD10",
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"PD11", "PD12", "PD13", "PD19", "PD20";
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function = "emac";
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drive-strength = <40>;
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};
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hdmi_pins: hdmi-pins {
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pins = "PH8", "PH9", "PH10";
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function = "hdmi";
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};
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mmc0_pins: mmc0-pins {
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pins = "PF0", "PF1", "PF2", "PF3",
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"PF4", "PF5";
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function = "mmc0";
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drive-strength = <30>;
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bias-pull-up;
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};
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/*
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* /omit-if-no-ref/ isn't supported by U-boot
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* keep this comment to avoid bad sync with Linux
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*/
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mmc1_pins: mmc1-pins {
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pins = "PG0", "PG1", "PG2", "PG3",
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"PG4", "PG5";
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function = "mmc1";
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drive-strength = <30>;
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bias-pull-up;
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};
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mmc2_pins: mmc2-pins {
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pins = "PC1", "PC4", "PC5", "PC6",
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"PC7", "PC8", "PC9", "PC10",
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"PC11", "PC12", "PC13", "PC14";
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function = "mmc2";
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drive-strength = <30>;
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bias-pull-up;
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};
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uart0_ph_pins: uart0-ph-pins {
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pins = "PH0", "PH1";
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function = "uart0";
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};
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};
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gic: interrupt-controller@3021000 {
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compatible = "arm,gic-400";
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reg = <0x03021000 0x1000>,
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<0x03022000 0x2000>,
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<0x03024000 0x2000>,
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<0x03026000 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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mmc0: mmc@4020000 {
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compatible = "allwinner,sun50i-h6-mmc",
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"allwinner,sun50i-a64-mmc";
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reg = <0x04020000 0x1000>;
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clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
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clock-names = "ahb", "mmc";
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resets = <&ccu RST_BUS_MMC0>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&mmc0_pins>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mmc1: mmc@4021000 {
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compatible = "allwinner,sun50i-h6-mmc",
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"allwinner,sun50i-a64-mmc";
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reg = <0x04021000 0x1000>;
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clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
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clock-names = "ahb", "mmc";
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resets = <&ccu RST_BUS_MMC1>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&mmc1_pins>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mmc2: mmc@4022000 {
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compatible = "allwinner,sun50i-h6-emmc",
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"allwinner,sun50i-a64-emmc";
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reg = <0x04022000 0x1000>;
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clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
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clock-names = "ahb", "mmc";
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resets = <&ccu RST_BUS_MMC2>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&mmc2_pins>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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uart0: serial@5000000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x05000000 0x400>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&ccu CLK_BUS_UART0>;
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resets = <&ccu RST_BUS_UART0>;
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status = "disabled";
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};
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uart1: serial@5000400 {
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compatible = "snps,dw-apb-uart";
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reg = <0x05000400 0x400>;
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interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&ccu CLK_BUS_UART1>;
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resets = <&ccu RST_BUS_UART1>;
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status = "disabled";
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};
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uart2: serial@5000800 {
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compatible = "snps,dw-apb-uart";
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reg = <0x05000800 0x400>;
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interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&ccu CLK_BUS_UART2>;
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resets = <&ccu RST_BUS_UART2>;
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status = "disabled";
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};
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uart3: serial@5000c00 {
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compatible = "snps,dw-apb-uart";
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reg = <0x05000c00 0x400>;
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&ccu CLK_BUS_UART3>;
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resets = <&ccu RST_BUS_UART3>;
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status = "disabled";
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};
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emac: ethernet@5020000 {
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compatible = "allwinner,sun50i-h6-emac",
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"allwinner,sun50i-a64-emac";
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syscon = <&syscon>;
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reg = <0x05020000 0x10000>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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resets = <&ccu RST_BUS_EMAC>;
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reset-names = "stmmaceth";
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clocks = <&ccu CLK_BUS_EMAC>;
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clock-names = "stmmaceth";
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status = "disabled";
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mdio: mdio {
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compatible = "snps,dwmac-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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usb2otg: usb@5100000 {
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compatible = "allwinner,sun50i-h6-musb",
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"allwinner,sun8i-a33-musb";
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reg = <0x05100000 0x0400>;
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clocks = <&ccu CLK_BUS_OTG>;
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resets = <&ccu RST_BUS_OTG>;
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interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "mc";
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phys = <&usb2phy 0>;
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phy-names = "usb";
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extcon = <&usb2phy 0>;
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status = "disabled";
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};
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usb2phy: phy@5100400 {
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compatible = "allwinner,sun50i-h6-usb-phy";
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reg = <0x05100400 0x24>,
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<0x05101800 0x4>,
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<0x05311800 0x4>;
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reg-names = "phy_ctrl",
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"pmu0",
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"pmu3";
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clocks = <&ccu CLK_USB_PHY0>,
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<&ccu CLK_USB_PHY3>;
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clock-names = "usb0_phy",
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"usb3_phy";
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resets = <&ccu RST_USB_PHY0>,
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<&ccu RST_USB_PHY3>;
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reset-names = "usb0_reset",
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"usb3_reset";
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status = "disabled";
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#phy-cells = <1>;
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};
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ehci0: usb@5101000 {
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compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
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reg = <0x05101000 0x100>;
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interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_OHCI0>,
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<&ccu CLK_BUS_EHCI0>,
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<&ccu CLK_USB_OHCI0>;
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resets = <&ccu RST_BUS_OHCI0>,
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<&ccu RST_BUS_EHCI0>;
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status = "disabled";
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};
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ohci0: usb@5101400 {
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compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
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reg = <0x05101400 0x100>;
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interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_OHCI0>,
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<&ccu CLK_USB_OHCI0>;
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resets = <&ccu RST_BUS_OHCI0>;
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status = "disabled";
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};
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ehci3: usb@5311000 {
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compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
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reg = <0x05311000 0x100>;
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interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_OHCI3>,
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<&ccu CLK_BUS_EHCI3>,
|
|
<&ccu CLK_USB_OHCI3>;
|
|
resets = <&ccu RST_BUS_OHCI3>,
|
|
<&ccu RST_BUS_EHCI3>;
|
|
phys = <&usb2phy 3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ohci3: usb@5311400 {
|
|
compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
|
|
reg = <0x05311400 0x100>;
|
|
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_BUS_OHCI3>,
|
|
<&ccu CLK_USB_OHCI3>;
|
|
resets = <&ccu RST_BUS_OHCI3>;
|
|
phys = <&usb2phy 3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
hdmi: hdmi@6000000 {
|
|
compatible = "allwinner,sun50i-h6-dw-hdmi";
|
|
reg = <0x06000000 0x10000>;
|
|
reg-io-width = <1>;
|
|
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
|
|
<&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>,
|
|
<&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>;
|
|
clock-names = "iahb", "isfr", "tmds", "cec", "hdcp",
|
|
"hdcp-bus";
|
|
resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>;
|
|
reset-names = "ctrl", "hdcp";
|
|
phys = <&hdmi_phy>;
|
|
phy-names = "hdmi-phy";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&hdmi_pins>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
hdmi_in: port@0 {
|
|
reg = <0>;
|
|
|
|
hdmi_in_tcon_top: endpoint {
|
|
remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
|
|
};
|
|
};
|
|
|
|
hdmi_out: port@1 {
|
|
reg = <1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
hdmi_phy: hdmi-phy@6010000 {
|
|
compatible = "allwinner,sun50i-h6-hdmi-phy";
|
|
reg = <0x06010000 0x10000>;
|
|
clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>;
|
|
clock-names = "bus", "mod";
|
|
resets = <&ccu RST_BUS_HDMI>;
|
|
reset-names = "phy";
|
|
#phy-cells = <0>;
|
|
};
|
|
|
|
tcon_top: tcon-top@6510000 {
|
|
compatible = "allwinner,sun50i-h6-tcon-top";
|
|
reg = <0x06510000 0x1000>;
|
|
clocks = <&ccu CLK_BUS_TCON_TOP>,
|
|
<&ccu CLK_TCON_TV0>;
|
|
clock-names = "bus",
|
|
"tcon-tv0";
|
|
clock-output-names = "tcon-top-tv0";
|
|
resets = <&ccu RST_BUS_TCON_TOP>;
|
|
reset-names = "rst";
|
|
#clock-cells = <1>;
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
tcon_top_mixer0_in: port@0 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0>;
|
|
|
|
tcon_top_mixer0_in_mixer0: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
|
|
};
|
|
};
|
|
|
|
tcon_top_mixer0_out: port@1 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <1>;
|
|
|
|
tcon_top_mixer0_out_tcon_tv: endpoint@2 {
|
|
reg = <2>;
|
|
remote-endpoint = <&tcon_tv_in_tcon_top_mixer0>;
|
|
};
|
|
};
|
|
|
|
tcon_top_hdmi_in: port@4 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <4>;
|
|
|
|
tcon_top_hdmi_in_tcon_tv: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&tcon_tv_out_tcon_top>;
|
|
};
|
|
};
|
|
|
|
tcon_top_hdmi_out: port@5 {
|
|
reg = <5>;
|
|
|
|
tcon_top_hdmi_out_hdmi: endpoint {
|
|
remote-endpoint = <&hdmi_in_tcon_top>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tcon_tv: lcd-controller@6515000 {
|
|
compatible = "allwinner,sun50i-h6-tcon-tv",
|
|
"allwinner,sun8i-r40-tcon-tv";
|
|
reg = <0x06515000 0x1000>;
|
|
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_BUS_TCON_TV0>,
|
|
<&tcon_top CLK_TCON_TOP_TV0>;
|
|
clock-names = "ahb",
|
|
"tcon-ch1";
|
|
resets = <&ccu RST_BUS_TCON_TV0>;
|
|
reset-names = "lcd";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
tcon_tv_in: port@0 {
|
|
reg = <0>;
|
|
|
|
tcon_tv_in_tcon_top_mixer0: endpoint {
|
|
remote-endpoint = <&tcon_top_mixer0_out_tcon_tv>;
|
|
};
|
|
};
|
|
|
|
tcon_tv_out: port@1 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <1>;
|
|
|
|
tcon_tv_out_tcon_top: endpoint@1 {
|
|
reg = <1>;
|
|
remote-endpoint = <&tcon_top_hdmi_in_tcon_tv>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
r_ccu: clock@7010000 {
|
|
compatible = "allwinner,sun50i-h6-r-ccu";
|
|
reg = <0x07010000 0x400>;
|
|
clocks = <&osc24M>, <&osc32k>, <&iosc>,
|
|
<&ccu CLK_PLL_PERIPH0>;
|
|
clock-names = "hosc", "losc", "iosc", "pll-periph";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
r_watchdog: watchdog@7020400 {
|
|
compatible = "allwinner,sun50i-h6-wdt",
|
|
"allwinner,sun6i-a31-wdt";
|
|
reg = <0x07020400 0x20>;
|
|
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
r_intc: interrupt-controller@7021000 {
|
|
compatible = "allwinner,sun50i-h6-r-intc",
|
|
"allwinner,sun6i-a31-r-intc";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x07021000 0x400>;
|
|
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
r_pio: pinctrl@7022000 {
|
|
compatible = "allwinner,sun50i-h6-r-pinctrl";
|
|
reg = <0x07022000 0x400>;
|
|
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&osc32k>;
|
|
clock-names = "apb", "hosc", "losc";
|
|
gpio-controller;
|
|
#gpio-cells = <3>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
|
|
r_i2c_pins: r-i2c-pins {
|
|
pins = "PL0", "PL1";
|
|
function = "s_i2c";
|
|
};
|
|
};
|
|
|
|
r_i2c: i2c@7081400 {
|
|
compatible = "allwinner,sun6i-a31-i2c";
|
|
reg = <0x07081400 0x400>;
|
|
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&r_ccu CLK_R_APB2_I2C>;
|
|
resets = <&r_ccu RST_R_APB2_I2C>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&r_i2c_pins>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
};
|
|
};
|