190 lines
3.4 KiB
Plaintext
190 lines
3.4 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2019 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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* Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
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*/
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#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
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/ {
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vddcpu_a: regulator-vddcpu-a {
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/*
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* MP8756GD Regulator.
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*/
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compatible = "pwm-regulator";
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regulator-name = "VDDCPU_A";
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regulator-min-microvolt = <690000>;
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regulator-max-microvolt = <1050000>;
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vin-supply = <&dc_in>;
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pwms = <&pwm_ab 0 1250 0>;
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pwm-dutycycle-range = <100 0>;
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regulator-boot-on;
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regulator-always-on;
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};
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vddcpu_b: regulator-vddcpu-b {
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/*
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* Silergy SY8030DEC Regulator.
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*/
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compatible = "pwm-regulator";
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regulator-name = "VDDCPU_B";
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regulator-min-microvolt = <690000>;
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regulator-max-microvolt = <1050000>;
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vin-supply = <&vsys_3v3>;
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pwms = <&pwm_AO_cd 1 1250 0>;
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pwm-dutycycle-range = <100 0>;
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regulator-boot-on;
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regulator-always-on;
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};
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sound {
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compatible = "amlogic,axg-sound-card";
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model = "G12A-KHADAS-VIM3";
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audio-aux-devs = <&tdmout_b>;
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audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
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"TDMOUT_B IN 1", "FRDDR_B OUT 1",
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"TDMOUT_B IN 2", "FRDDR_C OUT 1",
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"TDM_B Playback", "TDMOUT_B OUT";
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assigned-clocks = <&clkc CLKID_MPLL2>,
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<&clkc CLKID_MPLL0>,
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<&clkc CLKID_MPLL1>;
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assigned-clock-parents = <0>, <0>, <0>;
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assigned-clock-rates = <294912000>,
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<270950400>,
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<393216000>;
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status = "okay";
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dai-link-0 {
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sound-dai = <&frddr_a>;
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};
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dai-link-1 {
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sound-dai = <&frddr_b>;
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};
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dai-link-2 {
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sound-dai = <&frddr_c>;
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};
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/* 8ch hdmi interface */
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dai-link-3 {
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sound-dai = <&tdmif_b>;
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dai-format = "i2s";
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dai-tdm-slot-tx-mask-0 = <1 1>;
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dai-tdm-slot-tx-mask-1 = <1 1>;
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dai-tdm-slot-tx-mask-2 = <1 1>;
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dai-tdm-slot-tx-mask-3 = <1 1>;
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mclk-fs = <256>;
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codec {
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sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
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};
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};
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/* hdmi glue */
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dai-link-4 {
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sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
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codec {
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sound-dai = <&hdmi_tx>;
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};
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};
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};
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};
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&arb {
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status = "okay";
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};
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&clkc_audio {
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status = "okay";
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};
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&cpu0 {
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cpu-supply = <&vddcpu_b>;
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operating-points-v2 = <&cpu_opp_table_0>;
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clocks = <&clkc CLKID_CPU_CLK>;
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clock-latency = <50000>;
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};
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&cpu1 {
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cpu-supply = <&vddcpu_b>;
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operating-points-v2 = <&cpu_opp_table_0>;
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clocks = <&clkc CLKID_CPU_CLK>;
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clock-latency = <50000>;
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};
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&cpu100 {
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cpu-supply = <&vddcpu_a>;
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operating-points-v2 = <&cpub_opp_table_1>;
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clocks = <&clkc CLKID_CPUB_CLK>;
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clock-latency = <50000>;
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};
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&cpu101 {
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cpu-supply = <&vddcpu_a>;
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operating-points-v2 = <&cpub_opp_table_1>;
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clocks = <&clkc CLKID_CPUB_CLK>;
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clock-latency = <50000>;
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};
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&cpu102 {
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cpu-supply = <&vddcpu_a>;
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operating-points-v2 = <&cpub_opp_table_1>;
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clocks = <&clkc CLKID_CPUB_CLK>;
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clock-latency = <50000>;
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};
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&cpu103 {
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cpu-supply = <&vddcpu_a>;
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operating-points-v2 = <&cpub_opp_table_1>;
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clocks = <&clkc CLKID_CPUB_CLK>;
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clock-latency = <50000>;
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};
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&frddr_b {
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status = "okay";
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};
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&frddr_c {
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status = "okay";
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};
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&pwm_ab {
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pinctrl-0 = <&pwm_a_e_pins>;
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pinctrl-names = "default";
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clocks = <&xtal>;
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clock-names = "clkin0";
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status = "okay";
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};
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&pwm_AO_cd {
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pinctrl-0 = <&pwm_ao_d_e_pins>;
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pinctrl-names = "default";
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clocks = <&xtal>;
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clock-names = "clkin1";
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status = "okay";
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};
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&tdmif_b {
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status = "okay";
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};
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&tdmout_b {
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status = "okay";
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};
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&tohdmitx {
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status = "okay";
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};
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