403 lines
9.3 KiB
C
403 lines
9.3 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* PCI emulation device which swaps the case of text
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*
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* Copyright (c) 2014 Google, Inc
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* Written by Simon Glass <sjg@chromium.org>
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <pci.h>
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#include <asm/test.h>
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#include <linux/ctype.h>
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/**
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* struct swap_case_platdata - platform data for this device
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*
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* @command: Current PCI command value
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* @bar: Current base address values
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*/
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struct swap_case_platdata {
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u16 command;
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u32 bar[6];
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};
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enum {
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MEM_TEXT_SIZE = 0x100,
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};
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enum swap_case_op {
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OP_TO_LOWER,
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OP_TO_UPPER,
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OP_SWAP,
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};
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static struct pci_bar {
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int type;
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u32 size;
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} barinfo[] = {
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{ PCI_BASE_ADDRESS_SPACE_IO, 1 },
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{ PCI_BASE_ADDRESS_MEM_TYPE_32, MEM_TEXT_SIZE },
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{ 0, 0 },
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{ 0, 0 },
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{ 0, 0 },
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{ 0, 0 },
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};
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struct swap_case_priv {
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enum swap_case_op op;
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char mem_text[MEM_TEXT_SIZE];
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};
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static int sandbox_swap_case_use_ea(struct udevice *dev)
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{
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return !!ofnode_get_property(dev->node, "use-ea", NULL);
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}
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/* Please keep these macros in sync with ea_regs below */
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#define PCI_CAP_ID_EA_SIZE (sizeof(ea_regs) + 4)
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#define PCI_CAP_ID_EA_ENTRY_CNT 4
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/* Hardcoded EA structure, excluding 1st DW. */
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static const u32 ea_regs[] = {
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/* BEI=0, ES=2, BAR0 32b Base + 32b MaxOffset, I/O space */
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(2 << 8) | 2,
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PCI_CAP_EA_BASE_LO0,
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0,
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/* BEI=1, ES=2, BAR1 32b Base + 32b MaxOffset */
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(1 << 4) | 2,
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PCI_CAP_EA_BASE_LO1,
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MEM_TEXT_SIZE - 1,
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/* BEI=2, ES=3, BAR2 64b Base + 32b MaxOffset */
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(2 << 4) | 3,
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PCI_CAP_EA_BASE_LO2 | PCI_EA_IS_64,
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PCI_CAP_EA_SIZE_LO,
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PCI_CAP_EA_BASE_HI2,
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/* BEI=4, ES=4, BAR4 64b Base + 64b MaxOffset */
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(4 << 4) | 4,
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PCI_CAP_EA_BASE_LO4 | PCI_EA_IS_64,
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PCI_CAP_EA_SIZE_LO | PCI_EA_IS_64,
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PCI_CAP_EA_BASE_HI4,
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PCI_CAP_EA_SIZE_HI,
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};
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static int sandbox_swap_case_read_ea(struct udevice *emul, uint offset,
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ulong *valuep, enum pci_size_t size)
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{
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u32 reg;
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offset = offset - PCI_CAP_ID_EA_OFFSET - 4;
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reg = ea_regs[offset >> 2];
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reg >>= (offset % 4) * 8;
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*valuep = reg;
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return 0;
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}
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static int sandbox_swap_case_read_config(struct udevice *emul, uint offset,
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ulong *valuep, enum pci_size_t size)
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{
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struct swap_case_platdata *plat = dev_get_platdata(emul);
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/*
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* The content of the EA capability structure is handled elsewhere to
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* keep the switch/case below sane
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*/
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if (offset > PCI_CAP_ID_EA_OFFSET + PCI_CAP_LIST_NEXT &&
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offset < PCI_CAP_ID_EA_OFFSET + PCI_CAP_ID_EA_SIZE)
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return sandbox_swap_case_read_ea(emul, offset, valuep, size);
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switch (offset) {
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case PCI_COMMAND:
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*valuep = plat->command;
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break;
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case PCI_HEADER_TYPE:
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*valuep = 0;
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break;
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case PCI_VENDOR_ID:
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*valuep = SANDBOX_PCI_VENDOR_ID;
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break;
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case PCI_DEVICE_ID:
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*valuep = SANDBOX_PCI_SWAP_CASE_EMUL_ID;
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break;
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case PCI_CLASS_DEVICE:
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if (size == PCI_SIZE_8) {
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*valuep = SANDBOX_PCI_CLASS_SUB_CODE;
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} else {
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*valuep = (SANDBOX_PCI_CLASS_CODE << 8) |
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SANDBOX_PCI_CLASS_SUB_CODE;
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}
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break;
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case PCI_CLASS_CODE:
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*valuep = SANDBOX_PCI_CLASS_CODE;
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break;
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case PCI_BASE_ADDRESS_0:
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case PCI_BASE_ADDRESS_1:
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case PCI_BASE_ADDRESS_2:
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case PCI_BASE_ADDRESS_3:
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case PCI_BASE_ADDRESS_4:
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case PCI_BASE_ADDRESS_5: {
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int barnum;
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u32 *bar;
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barnum = pci_offset_to_barnum(offset);
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bar = &plat->bar[barnum];
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*valuep = sandbox_pci_read_bar(*bar, barinfo[barnum].type,
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barinfo[barnum].size);
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break;
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}
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case PCI_CAPABILITY_LIST:
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*valuep = PCI_CAP_ID_PM_OFFSET;
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break;
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case PCI_CAP_ID_PM_OFFSET:
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*valuep = (PCI_CAP_ID_EXP_OFFSET << 8) | PCI_CAP_ID_PM;
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break;
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case PCI_CAP_ID_PM_OFFSET + PCI_CAP_LIST_NEXT:
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*valuep = PCI_CAP_ID_EXP_OFFSET;
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break;
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case PCI_CAP_ID_EXP_OFFSET:
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*valuep = (PCI_CAP_ID_MSIX_OFFSET << 8) | PCI_CAP_ID_EXP;
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break;
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case PCI_CAP_ID_EXP_OFFSET + PCI_CAP_LIST_NEXT:
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*valuep = PCI_CAP_ID_MSIX_OFFSET;
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break;
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case PCI_CAP_ID_MSIX_OFFSET:
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if (sandbox_swap_case_use_ea(emul))
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*valuep = (PCI_CAP_ID_EA_OFFSET << 8) | PCI_CAP_ID_MSIX;
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else
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*valuep = PCI_CAP_ID_MSIX;
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break;
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case PCI_CAP_ID_MSIX_OFFSET + PCI_CAP_LIST_NEXT:
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if (sandbox_swap_case_use_ea(emul))
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*valuep = PCI_CAP_ID_EA_OFFSET;
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else
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*valuep = 0;
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break;
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case PCI_CAP_ID_EA_OFFSET:
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*valuep = (PCI_CAP_ID_EA_ENTRY_CNT << 16) | PCI_CAP_ID_EA;
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break;
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case PCI_CAP_ID_EA_OFFSET + PCI_CAP_LIST_NEXT:
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*valuep = 0;
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break;
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case PCI_EXT_CAP_ID_ERR_OFFSET:
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*valuep = (PCI_EXT_CAP_ID_VC_OFFSET << 20) | PCI_EXT_CAP_ID_ERR;
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break;
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case PCI_EXT_CAP_ID_VC_OFFSET:
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*valuep = (PCI_EXT_CAP_ID_DSN_OFFSET << 20) | PCI_EXT_CAP_ID_VC;
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break;
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case PCI_EXT_CAP_ID_DSN_OFFSET:
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*valuep = PCI_EXT_CAP_ID_DSN;
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break;
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}
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return 0;
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}
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static int sandbox_swap_case_write_config(struct udevice *emul, uint offset,
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ulong value, enum pci_size_t size)
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{
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struct swap_case_platdata *plat = dev_get_platdata(emul);
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switch (offset) {
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case PCI_COMMAND:
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plat->command = value;
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break;
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case PCI_BASE_ADDRESS_0:
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case PCI_BASE_ADDRESS_1: {
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int barnum;
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u32 *bar;
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barnum = pci_offset_to_barnum(offset);
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bar = &plat->bar[barnum];
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debug("w bar %d=%lx\n", barnum, value);
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*bar = value;
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/* space indicator (bit#0) is read-only */
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*bar |= barinfo[barnum].type;
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break;
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}
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}
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return 0;
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}
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static int sandbox_swap_case_find_bar(struct udevice *emul, unsigned int addr,
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int *barnump, unsigned int *offsetp)
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{
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struct swap_case_platdata *plat = dev_get_platdata(emul);
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int barnum;
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for (barnum = 0; barnum < ARRAY_SIZE(barinfo); barnum++) {
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unsigned int size = barinfo[barnum].size;
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u32 base = plat->bar[barnum] & ~PCI_BASE_ADDRESS_SPACE;
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if (addr >= base && addr < base + size) {
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*barnump = barnum;
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*offsetp = addr - base;
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return 0;
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}
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}
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*barnump = -1;
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return -ENOENT;
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}
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static void sandbox_swap_case_do_op(enum swap_case_op op, char *str, int len)
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{
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for (; len > 0; len--, str++) {
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switch (op) {
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case OP_TO_UPPER:
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*str = toupper(*str);
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break;
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case OP_TO_LOWER:
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*str = tolower(*str);
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break;
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case OP_SWAP:
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if (isupper(*str))
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*str = tolower(*str);
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else
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*str = toupper(*str);
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break;
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}
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}
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}
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static int sandbox_swap_case_read_io(struct udevice *dev, unsigned int addr,
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ulong *valuep, enum pci_size_t size)
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{
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struct swap_case_priv *priv = dev_get_priv(dev);
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unsigned int offset;
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int barnum;
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int ret;
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ret = sandbox_swap_case_find_bar(dev, addr, &barnum, &offset);
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if (ret)
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return ret;
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if (barnum == 0 && offset == 0)
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*valuep = (*valuep & ~0xff) | priv->op;
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return 0;
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}
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static int sandbox_swap_case_write_io(struct udevice *dev, unsigned int addr,
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ulong value, enum pci_size_t size)
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{
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struct swap_case_priv *priv = dev_get_priv(dev);
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unsigned int offset;
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int barnum;
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int ret;
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ret = sandbox_swap_case_find_bar(dev, addr, &barnum, &offset);
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if (ret)
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return ret;
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if (barnum == 0 && offset == 0)
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priv->op = value;
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return 0;
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}
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static int pci_ea_bar2_magic = PCI_EA_BAR2_MAGIC;
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static int pci_ea_bar4_magic = PCI_EA_BAR4_MAGIC;
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static int sandbox_swap_case_map_physmem(struct udevice *dev,
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phys_addr_t addr, unsigned long *lenp, void **ptrp)
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{
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struct swap_case_priv *priv = dev_get_priv(dev);
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unsigned int offset, avail;
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int barnum;
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int ret;
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if (sandbox_swap_case_use_ea(dev)) {
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/*
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* only support mapping base address in EA test for now, we
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* don't handle mapping an offset inside a BAR. Seems good
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* enough for the current test.
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*/
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switch (addr) {
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case (phys_addr_t)PCI_CAP_EA_BASE_LO0:
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*ptrp = &priv->op;
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*lenp = 4;
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break;
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case (phys_addr_t)PCI_CAP_EA_BASE_LO1:
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*ptrp = priv->mem_text;
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*lenp = barinfo[1].size - 1;
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break;
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case (phys_addr_t)((PCI_CAP_EA_BASE_HI2 << 32) |
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PCI_CAP_EA_BASE_LO2):
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*ptrp = &pci_ea_bar2_magic;
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*lenp = PCI_CAP_EA_SIZE_LO;
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break;
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case (phys_addr_t)((PCI_CAP_EA_BASE_HI4 << 32) |
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PCI_CAP_EA_BASE_LO4):
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*ptrp = &pci_ea_bar4_magic;
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*lenp = (PCI_CAP_EA_SIZE_HI << 32) |
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PCI_CAP_EA_SIZE_LO;
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break;
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default:
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return -ENOENT;
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}
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return 0;
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}
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ret = sandbox_swap_case_find_bar(dev, addr, &barnum, &offset);
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if (ret)
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return ret;
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if (barnum == 1) {
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*ptrp = priv->mem_text + offset;
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avail = barinfo[1].size - offset;
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if (avail > barinfo[1].size)
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*lenp = 0;
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else
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*lenp = min(*lenp, (ulong)avail);
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return 0;
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}
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return -ENOENT;
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}
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static int sandbox_swap_case_unmap_physmem(struct udevice *dev,
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const void *vaddr, unsigned long len)
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{
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struct swap_case_priv *priv = dev_get_priv(dev);
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sandbox_swap_case_do_op(priv->op, (void *)vaddr, len);
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return 0;
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}
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|
static struct dm_pci_emul_ops sandbox_swap_case_emul_ops = {
|
||
|
|
.read_config = sandbox_swap_case_read_config,
|
||
|
|
.write_config = sandbox_swap_case_write_config,
|
||
|
|
.read_io = sandbox_swap_case_read_io,
|
||
|
|
.write_io = sandbox_swap_case_write_io,
|
||
|
|
.map_physmem = sandbox_swap_case_map_physmem,
|
||
|
|
.unmap_physmem = sandbox_swap_case_unmap_physmem,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct udevice_id sandbox_swap_case_ids[] = {
|
||
|
|
{ .compatible = "sandbox,swap-case" },
|
||
|
|
{ }
|
||
|
|
};
|
||
|
|
|
||
|
|
U_BOOT_DRIVER(sandbox_swap_case_emul) = {
|
||
|
|
.name = "sandbox_swap_case_emul",
|
||
|
|
.id = UCLASS_PCI_EMUL,
|
||
|
|
.of_match = sandbox_swap_case_ids,
|
||
|
|
.ops = &sandbox_swap_case_emul_ops,
|
||
|
|
.priv_auto_alloc_size = sizeof(struct swap_case_priv),
|
||
|
|
.platdata_auto_alloc_size = sizeof(struct swap_case_platdata),
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct pci_device_id sandbox_swap_case_supported[] = {
|
||
|
|
{ PCI_VDEVICE(SANDBOX, SANDBOX_PCI_SWAP_CASE_EMUL_ID),
|
||
|
|
SWAP_CASE_DRV_DATA },
|
||
|
|
{},
|
||
|
|
};
|
||
|
|
|
||
|
|
U_BOOT_PCI_DEVICE(sandbox_swap_case_emul, sandbox_swap_case_supported);
|