86 lines
1.6 KiB
C
86 lines
1.6 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* PPC-AG BG0900 board
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*
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* Copyright (C) 2013 Marek Vasut <marex@denx.de>
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*/
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#include <common.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux-mx28.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#include <linux/mii.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <errno.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Functions
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*/
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int board_early_init_f(void)
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{
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/* IO0 clock at 480MHz */
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mxs_set_ioclk(MXC_IOCLK0, 480000);
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/* IO1 clock at 480MHz */
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mxs_set_ioclk(MXC_IOCLK1, 480000);
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/* SSP2 clock at 160MHz */
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mxs_set_sspclk(MXC_SSPCLK2, 160000, 0);
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return 0;
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}
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int dram_init(void)
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{
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return mxs_dram_init();
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}
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int board_init(void)
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{
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/* Adress of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
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return 0;
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}
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#ifdef CONFIG_CMD_NET
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int board_eth_init(bd_t *bis)
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{
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struct mxs_clkctrl_regs *clkctrl_regs =
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(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
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struct eth_device *dev;
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int ret;
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ret = cpu_eth_init(bis);
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/* BG0900 uses ENET_CLK PAD to drive FEC clock */
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writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN,
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&clkctrl_regs->hw_clkctrl_enet);
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/* Reset FEC PHYs */
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gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0);
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udelay(200);
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gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1);
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ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
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if (ret) {
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puts("FEC MXS: Unable to init FEC0\n");
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return ret;
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}
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dev = eth_get_dev_by_name("FEC0");
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if (!dev) {
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puts("FEC MXS: Unable to get FEC0 device entry\n");
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return -EINVAL;
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}
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return ret;
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}
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#endif
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