72 lines
1.3 KiB
C
72 lines
1.3 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019 Linaro Ltd.
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* Copyright (C) 2016 NXP Semiconductors
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*/
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/mx7-pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/io.h>
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#include <common.h>
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#include <linux/sizes.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
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PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
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static iomux_v3_cfg_t const meerkat96_pads[] = {
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/* UART6 as debug serial */
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MX7D_PAD_SD1_CD_B__UART6_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX7D_PAD_SD1_WP__UART6_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
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/* WDOG1 for reset */
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MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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int dram_init(void)
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{
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gd->ram_size = PHYS_SDRAM_SIZE;
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return 0;
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}
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int board_early_init_f(void)
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{
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imx_iomux_v3_setup_multiple_pads(meerkat96_pads,
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ARRAY_SIZE(meerkat96_pads));
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return 0;
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}
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int board_init(void)
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{
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/* address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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return 0;
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}
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int checkboard(void)
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{
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char *mode;
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if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT))
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mode = "secure";
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else
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mode = "non-secure";
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printf("Board: i.MX7D Meerkat96 in %s mode\n", mode);
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return 0;
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}
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int board_late_init(void)
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{
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set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR);
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return 0;
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}
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