488 lines
11 KiB
C
488 lines
11 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2015 Linaro
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* Peter Griffin <peter.griffin@linaro.org>
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*/
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#include <common.h>
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#include <dm.h>
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#include <dm/platform_data/serial_pl01x.h>
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#include <errno.h>
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#include <malloc.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <usb.h>
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#include <power/hi6553_pmic.h>
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#include <asm-generic/gpio.h>
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#include <asm/arch/dwmmc.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/periph.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/hi6220.h>
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#include <asm/armv8/mmu.h>
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/*TODO drop this table in favour of device tree */
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static const struct hikey_gpio_platdata hi6220_gpio[] = {
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{ 0, HI6220_GPIO_BASE(0)},
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{ 1, HI6220_GPIO_BASE(1)},
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{ 2, HI6220_GPIO_BASE(2)},
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{ 3, HI6220_GPIO_BASE(3)},
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{ 4, HI6220_GPIO_BASE(4)},
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{ 5, HI6220_GPIO_BASE(5)},
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{ 6, HI6220_GPIO_BASE(6)},
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{ 7, HI6220_GPIO_BASE(7)},
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{ 8, HI6220_GPIO_BASE(8)},
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{ 9, HI6220_GPIO_BASE(9)},
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{ 10, HI6220_GPIO_BASE(10)},
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{ 11, HI6220_GPIO_BASE(11)},
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{ 12, HI6220_GPIO_BASE(12)},
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{ 13, HI6220_GPIO_BASE(13)},
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{ 14, HI6220_GPIO_BASE(14)},
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{ 15, HI6220_GPIO_BASE(15)},
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{ 16, HI6220_GPIO_BASE(16)},
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{ 17, HI6220_GPIO_BASE(17)},
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{ 18, HI6220_GPIO_BASE(18)},
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{ 19, HI6220_GPIO_BASE(19)},
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};
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U_BOOT_DEVICES(hi6220_gpios) = {
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{ "gpio_hi6220", &hi6220_gpio[0] },
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{ "gpio_hi6220", &hi6220_gpio[1] },
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{ "gpio_hi6220", &hi6220_gpio[2] },
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{ "gpio_hi6220", &hi6220_gpio[3] },
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{ "gpio_hi6220", &hi6220_gpio[4] },
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{ "gpio_hi6220", &hi6220_gpio[5] },
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{ "gpio_hi6220", &hi6220_gpio[6] },
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{ "gpio_hi6220", &hi6220_gpio[7] },
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{ "gpio_hi6220", &hi6220_gpio[8] },
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{ "gpio_hi6220", &hi6220_gpio[9] },
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{ "gpio_hi6220", &hi6220_gpio[10] },
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{ "gpio_hi6220", &hi6220_gpio[11] },
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{ "gpio_hi6220", &hi6220_gpio[12] },
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{ "gpio_hi6220", &hi6220_gpio[13] },
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{ "gpio_hi6220", &hi6220_gpio[14] },
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{ "gpio_hi6220", &hi6220_gpio[15] },
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{ "gpio_hi6220", &hi6220_gpio[16] },
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{ "gpio_hi6220", &hi6220_gpio[17] },
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{ "gpio_hi6220", &hi6220_gpio[18] },
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{ "gpio_hi6220", &hi6220_gpio[19] },
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};
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DECLARE_GLOBAL_DATA_PTR;
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#if !CONFIG_IS_ENABLED(OF_CONTROL)
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static const struct pl01x_serial_platdata serial_platdata = {
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#if CONFIG_CONS_INDEX == 1
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.base = HI6220_UART0_BASE,
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#elif CONFIG_CONS_INDEX == 4
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.base = HI6220_UART3_BASE,
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#else
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#error "Unsupported console index value."
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#endif
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.type = TYPE_PL011,
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.clock = 19200000
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};
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U_BOOT_DEVICE(hikey_seriala) = {
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.name = "serial_pl01x",
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.platdata = &serial_platdata,
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};
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#endif
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static struct mm_region hikey_mem_map[] = {
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{
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.virt = 0x0UL,
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.phys = 0x0UL,
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.size = 0x80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = 0x80000000UL,
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.phys = 0x80000000UL,
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.size = 0x80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = hikey_mem_map;
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#ifdef CONFIG_BOARD_EARLY_INIT_F
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int board_uart_init(void)
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{
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switch (CONFIG_CONS_INDEX) {
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case 1:
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hi6220_pinmux_config(PERIPH_ID_UART0);
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break;
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case 4:
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hi6220_pinmux_config(PERIPH_ID_UART3);
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break;
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default:
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debug("%s: Unsupported UART selected\n", __func__);
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return -1;
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}
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return 0;
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}
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int board_early_init_f(void)
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{
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board_uart_init();
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return 0;
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}
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#endif
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struct peri_sc_periph_regs *peri_sc =
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(struct peri_sc_periph_regs *)HI6220_PERI_BASE;
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struct alwayson_sc_regs *ao_sc =
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(struct alwayson_sc_regs *)ALWAYSON_CTRL_BASE;
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/* status offset from enable reg */
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#define STAT_EN_OFF 0x2
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void hi6220_clk_enable(u32 bitfield, unsigned int *clk_base)
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{
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uint32_t data;
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data = readl(clk_base);
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data |= bitfield;
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writel(bitfield, clk_base);
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do {
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data = readl(clk_base + STAT_EN_OFF);
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} while ((data & bitfield) == 0);
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}
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/* status offset from disable reg */
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#define STAT_DIS_OFF 0x1
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void hi6220_clk_disable(u32 bitfield, unsigned int *clk_base)
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{
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uint32_t data;
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data = readl(clk_base);
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data |= bitfield;
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writel(data, clk_base);
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do {
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data = readl(clk_base + STAT_DIS_OFF);
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} while (data & bitfield);
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}
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#define EYE_PATTERN 0x70533483
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int board_usb_init(int index, enum usb_init_type init)
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{
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unsigned int data;
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/* enable USB clock */
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hi6220_clk_enable(PERI_CLK0_USBOTG, &peri_sc->clk0_en);
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/* take usb IPs out of reset */
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writel(PERI_RST0_USBOTG_BUS | PERI_RST0_POR_PICOPHY |
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PERI_RST0_USBOTG | PERI_RST0_USBOTG_32K,
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&peri_sc->rst0_dis);
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do {
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data = readl(&peri_sc->rst0_stat);
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data &= PERI_RST0_USBOTG_BUS | PERI_RST0_POR_PICOPHY |
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PERI_RST0_USBOTG | PERI_RST0_USBOTG_32K;
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} while (data);
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/*CTRL 5*/
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data = readl(&peri_sc->ctrl5);
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data &= ~PERI_CTRL5_PICOPHY_BC_MODE;
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data |= PERI_CTRL5_USBOTG_RES_SEL | PERI_CTRL5_PICOPHY_ACAENB;
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data |= 0x300;
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writel(data, &peri_sc->ctrl5);
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/*CTRL 4*/
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/* configure USB PHY */
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data = readl(&peri_sc->ctrl4);
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/* make PHY out of low power mode */
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data &= ~PERI_CTRL4_PICO_SIDDQ;
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data &= ~PERI_CTRL4_PICO_OGDISABLE;
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data |= PERI_CTRL4_PICO_VBUSVLDEXTSEL | PERI_CTRL4_PICO_VBUSVLDEXT;
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writel(data, &peri_sc->ctrl4);
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writel(EYE_PATTERN, &peri_sc->ctrl8);
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mdelay(5);
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return 0;
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}
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static int config_sd_carddetect(void)
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{
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int ret;
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/* configure GPIO8 as nopull */
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writel(0, 0xf8001830);
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gpio_request(8, "SD CD");
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gpio_direction_input(8);
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ret = gpio_get_value(8);
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if (!ret) {
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printf("%s: SD card present\n", __func__);
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return 1;
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}
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printf("%s: SD card not present\n", __func__);
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return 0;
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}
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static void mmc1_init_pll(void)
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{
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uint32_t data;
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/* select SYSPLL as the source of MMC1 */
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/* select SYSPLL as the source of MUX1 (SC_CLK_SEL0) */
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writel(1 << 11 | 1 << 27, &peri_sc->clk0_sel);
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do {
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data = readl(&peri_sc->clk0_sel);
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} while (!(data & (1 << 11)));
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/* select MUX1 as the source of MUX2 (SC_CLK_SEL0) */
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writel(1 << 30, &peri_sc->clk0_sel);
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do {
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data = readl(&peri_sc->clk0_sel);
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} while (data & (1 << 14));
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hi6220_clk_enable(PERI_CLK0_MMC1, &peri_sc->clk0_en);
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hi6220_clk_enable(PERI_CLK12_MMC1_SRC, &peri_sc->clk12_en);
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do {
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/* 1.2GHz / 50 = 24MHz */
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writel(0x31 | (1 << 7), &peri_sc->clkcfg8bit2);
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data = readl(&peri_sc->clkcfg8bit2);
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} while ((data & 0x31) != 0x31);
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}
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static void mmc1_reset_clk(void)
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{
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unsigned int data;
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/* disable mmc1 bus clock */
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hi6220_clk_disable(PERI_CLK0_MMC1, &peri_sc->clk0_dis);
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/* enable mmc1 bus clock */
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hi6220_clk_enable(PERI_CLK0_MMC1, &peri_sc->clk0_en);
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/* reset mmc1 clock domain */
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writel(PERI_RST0_MMC1, &peri_sc->rst0_en);
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/* bypass mmc1 clock phase */
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data = readl(&peri_sc->ctrl2);
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data |= 3 << 2;
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writel(data, &peri_sc->ctrl2);
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/* disable low power */
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data = readl(&peri_sc->ctrl13);
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data |= 1 << 4;
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writel(data, &peri_sc->ctrl13);
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do {
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data = readl(&peri_sc->rst0_stat);
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} while (!(data & PERI_RST0_MMC1));
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/* unreset mmc1 clock domain */
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writel(PERI_RST0_MMC1, &peri_sc->rst0_dis);
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do {
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data = readl(&peri_sc->rst0_stat);
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} while (data & PERI_RST0_MMC1);
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}
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static void mmc0_reset_clk(void)
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{
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unsigned int data;
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/* disable mmc0 bus clock */
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hi6220_clk_disable(PERI_CLK0_MMC0, &peri_sc->clk0_dis);
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/* enable mmc0 bus clock */
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hi6220_clk_enable(PERI_CLK0_MMC0, &peri_sc->clk0_en);
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/* reset mmc0 clock domain */
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writel(PERI_RST0_MMC0, &peri_sc->rst0_en);
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/* bypass mmc0 clock phase */
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data = readl(&peri_sc->ctrl2);
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data |= 3;
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writel(data, &peri_sc->ctrl2);
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/* disable low power */
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data = readl(&peri_sc->ctrl13);
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data |= 1 << 3;
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writel(data, &peri_sc->ctrl13);
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do {
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data = readl(&peri_sc->rst0_stat);
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} while (!(data & PERI_RST0_MMC0));
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/* unreset mmc0 clock domain */
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writel(PERI_RST0_MMC0, &peri_sc->rst0_dis);
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do {
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data = readl(&peri_sc->rst0_stat);
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} while (data & PERI_RST0_MMC0);
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}
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/* PMU SSI is the IP that maps the external PMU hi6553 registers as IO */
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static void hi6220_pmussi_init(void)
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{
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uint32_t data;
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/* Take PMUSSI out of reset */
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writel(ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_PMUSSI_N,
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&ao_sc->rst4_dis);
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do {
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data = readl(&ao_sc->rst4_stat);
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} while (data & ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_PMUSSI_N);
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/* set PMU SSI clock latency for read operation */
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data = readl(&ao_sc->mcu_subsys_ctrl3);
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data &= ~ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_MASK;
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data |= ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_3;
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writel(data, &ao_sc->mcu_subsys_ctrl3);
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/* enable PMUSSI clock */
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data = ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_CCPU |
|
||
|
|
ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_MCU;
|
||
|
|
|
||
|
|
hi6220_clk_enable(data, &ao_sc->clk5_en);
|
||
|
|
|
||
|
|
/* Output high to PMIC on PWR_HOLD_GPIO0_0 */
|
||
|
|
gpio_request(0, "PWR_HOLD_GPIO0_0");
|
||
|
|
gpio_direction_output(0, 1);
|
||
|
|
}
|
||
|
|
|
||
|
|
int misc_init_r(void)
|
||
|
|
{
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
int board_init(void)
|
||
|
|
{
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
#ifdef CONFIG_MMC
|
||
|
|
|
||
|
|
static int init_dwmmc(void)
|
||
|
|
{
|
||
|
|
int ret = 0;
|
||
|
|
|
||
|
|
#ifdef CONFIG_MMC_DW
|
||
|
|
|
||
|
|
/* mmc0 pll is already configured by ATF */
|
||
|
|
mmc0_reset_clk();
|
||
|
|
ret = hi6220_pinmux_config(PERIPH_ID_SDMMC0);
|
||
|
|
if (ret)
|
||
|
|
printf("%s: Error configuring pinmux for eMMC (%d)\n"
|
||
|
|
, __func__, ret);
|
||
|
|
|
||
|
|
ret |= hi6220_dwmci_add_port(0, HI6220_MMC0_BASE, 8);
|
||
|
|
if (ret)
|
||
|
|
printf("%s: Error adding eMMC port (%d)\n", __func__, ret);
|
||
|
|
|
||
|
|
|
||
|
|
/* take mmc1 (sd slot) out of reset, configure clocks and pinmuxing */
|
||
|
|
mmc1_init_pll();
|
||
|
|
mmc1_reset_clk();
|
||
|
|
|
||
|
|
ret |= hi6220_pinmux_config(PERIPH_ID_SDMMC1);
|
||
|
|
if (ret)
|
||
|
|
printf("%s: Error configuring pinmux for eMMC (%d)\n"
|
||
|
|
, __func__, ret);
|
||
|
|
|
||
|
|
config_sd_carddetect();
|
||
|
|
|
||
|
|
ret |= hi6220_dwmci_add_port(1, HI6220_MMC1_BASE, 4);
|
||
|
|
if (ret)
|
||
|
|
printf("%s: Error adding SD port (%d)\n", __func__, ret);
|
||
|
|
|
||
|
|
#endif
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* setup board specific PMIC */
|
||
|
|
int power_init_board(void)
|
||
|
|
{
|
||
|
|
/* init the hi6220 pmussi ip */
|
||
|
|
hi6220_pmussi_init();
|
||
|
|
|
||
|
|
power_hi6553_init((u8 *)HI6220_PMUSSI_BASE);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
int board_mmc_init(bd_t *bis)
|
||
|
|
{
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
/* add the eMMC and sd ports */
|
||
|
|
ret = init_dwmmc();
|
||
|
|
|
||
|
|
if (ret)
|
||
|
|
debug("init_dwmmc failed\n");
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
int dram_init(void)
|
||
|
|
{
|
||
|
|
gd->ram_size = PHYS_SDRAM_1_SIZE;
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
int dram_init_banksize(void)
|
||
|
|
{
|
||
|
|
/*
|
||
|
|
* Reserve regions below from DT memory node (which gets generated
|
||
|
|
* by U-Boot from the dram banks in arch_fixup_fdt() before booting
|
||
|
|
* the kernel. This will then match the kernel hikey dts memory node.
|
||
|
|
*
|
||
|
|
* 0x05e0,0000 - 0x05ef,ffff: MCU firmware runtime using
|
||
|
|
* 0x05f0,1000 - 0x05f0,1fff: Reboot reason
|
||
|
|
* 0x06df,f000 - 0x06df,ffff: Mailbox message data
|
||
|
|
* 0x0740,f000 - 0x0740,ffff: MCU firmware section
|
||
|
|
* 0x21f0,0000 - 0x21ff,ffff: pstore/ramoops buffer
|
||
|
|
* 0x3e00,0000 - 0x3fff,ffff: OP-TEE
|
||
|
|
*/
|
||
|
|
|
||
|
|
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
|
||
|
|
gd->bd->bi_dram[0].size = 0x05e00000;
|
||
|
|
|
||
|
|
gd->bd->bi_dram[1].start = 0x05f00000;
|
||
|
|
gd->bd->bi_dram[1].size = 0x00001000;
|
||
|
|
|
||
|
|
gd->bd->bi_dram[2].start = 0x05f02000;
|
||
|
|
gd->bd->bi_dram[2].size = 0x00efd000;
|
||
|
|
|
||
|
|
gd->bd->bi_dram[3].start = 0x06e00000;
|
||
|
|
gd->bd->bi_dram[3].size = 0x0060f000;
|
||
|
|
|
||
|
|
gd->bd->bi_dram[4].start = 0x07410000;
|
||
|
|
gd->bd->bi_dram[4].size = 0x1aaf0000;
|
||
|
|
|
||
|
|
gd->bd->bi_dram[5].start = 0x22000000;
|
||
|
|
gd->bd->bi_dram[5].size = 0x1c000000;
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
void reset_cpu(ulong addr)
|
||
|
|
{
|
||
|
|
writel(0x48698284, &ao_sc->stat0);
|
||
|
|
wfi();
|
||
|
|
}
|