344 lines
10 KiB
C
344 lines
10 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2015, Freescale Semiconductor, Inc.
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*/
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/mc_cgm_regs.h>
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#include <asm/arch/mc_me_regs.h>
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#include <asm/arch/clock.h>
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/*
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* Select the clock reference for required pll.
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* pll - ARM_PLL, PERIPH_PLL, ENET_PLL, DDR_PLL, VIDEO_PLL.
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* refclk_freq - input referece clock frequency (FXOSC - 40 MHZ, FIRC - 48 MHZ)
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*/
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static int select_pll_source_clk(enum pll_type pll, u32 refclk_freq)
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{
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u32 clk_src;
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u32 pll_idx;
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volatile struct src *src = (struct src *)SRC_SOC_BASE_ADDR;
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/* select the pll clock source */
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switch (refclk_freq) {
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case FIRC_CLK_FREQ:
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clk_src = SRC_GPR1_FIRC_CLK_SOURCE;
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break;
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case XOSC_CLK_FREQ:
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clk_src = SRC_GPR1_XOSC_CLK_SOURCE;
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break;
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default:
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/* The clock frequency for the source clock is unknown */
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return -1;
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}
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/*
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* The hardware definition is not uniform, it has to calculate again
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* the recurrence formula.
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*/
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switch (pll) {
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case PERIPH_PLL:
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pll_idx = 3;
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break;
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case ENET_PLL:
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pll_idx = 1;
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break;
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case DDR_PLL:
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pll_idx = 2;
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break;
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default:
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pll_idx = pll;
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}
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writel(readl(&src->gpr1) | SRC_GPR1_PLL_SOURCE(pll_idx, clk_src),
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&src->gpr1);
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return 0;
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}
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static void entry_to_target_mode(u32 mode)
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{
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writel(mode | MC_ME_MCTL_KEY, MC_ME_MCTL);
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writel(mode | MC_ME_MCTL_INVERTEDKEY, MC_ME_MCTL);
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while ((readl(MC_ME_GS) & MC_ME_GS_S_MTRANS) != 0x00000000) ;
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}
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/*
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* Program the pll according to the input parameters.
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* pll - ARM_PLL, PERIPH_PLL, ENET_PLL, DDR_PLL, VIDEO_PLL.
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* refclk_freq - input reference clock frequency (FXOSC - 40 MHZ, FIRC - 48 MHZ)
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* freq - expected output frequency for PHY0
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* freq1 - expected output frequency for PHY1
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* dfs_nr - number of DFS modules for current PLL
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* dfs - array with the activation dfs field, mfn and mfi
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* plldv_prediv - divider of clkfreq_ref
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* plldv_mfd - loop multiplication factor divider
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* pllfd_mfn - numerator loop multiplication factor divider
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* Please consult the PLLDIG chapter of platform manual
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* before to use this function.
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*)
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*/
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static int program_pll(enum pll_type pll, u32 refclk_freq, u32 freq0, u32 freq1,
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u32 dfs_nr, u32 dfs[][DFS_PARAMS_Nr], u32 plldv_prediv,
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u32 plldv_mfd, u32 pllfd_mfn)
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{
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u32 i, rfdphi1, rfdphi, dfs_on = 0, fvco;
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/*
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* This formula is from platform reference manual (Rev. 1, 6/2015), PLLDIG chapter.
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*/
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fvco =
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(refclk_freq / plldv_prediv) * (plldv_mfd +
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pllfd_mfn / (float)20480);
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/*
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* VCO should have value in [ PLL_MIN_FREQ, PLL_MAX_FREQ ]. Please consult
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* the platform DataSheet in order to determine the allowed values.
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*/
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if (fvco < PLL_MIN_FREQ || fvco > PLL_MAX_FREQ) {
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return -1;
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}
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if (select_pll_source_clk(pll, refclk_freq) < 0) {
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return -1;
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}
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rfdphi = fvco / freq0;
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rfdphi1 = (freq1 == 0) ? 0 : fvco / freq1;
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writel(PLLDIG_PLLDV_RFDPHI1_SET(rfdphi1) |
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PLLDIG_PLLDV_RFDPHI_SET(rfdphi) |
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PLLDIG_PLLDV_PREDIV_SET(plldv_prediv) |
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PLLDIG_PLLDV_MFD(plldv_mfd), PLLDIG_PLLDV(pll));
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writel(readl(PLLDIG_PLLFD(pll)) | PLLDIG_PLLFD_MFN_SET(pllfd_mfn) |
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PLLDIG_PLLFD_SMDEN, PLLDIG_PLLFD(pll));
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/* switch on the pll in current mode */
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writel(readl(MC_ME_RUNn_MC(0)) | MC_ME_RUNMODE_MC_PLL(pll),
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MC_ME_RUNn_MC(0));
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entry_to_target_mode(MC_ME_MCTL_RUN0);
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/* Only ARM_PLL, ENET_PLL and DDR_PLL */
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if ((pll == ARM_PLL) || (pll == ENET_PLL) || (pll == DDR_PLL)) {
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/* DFS clk enable programming */
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writel(DFS_CTRL_DLL_RESET, DFS_CTRL(pll));
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writel(DFS_DLLPRG1_CPICTRL_SET(0x5) |
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DFS_DLLPRG1_VSETTLCTRL_SET(0x1) |
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DFS_DLLPRG1_CALBYPEN_SET(0x0) |
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DFS_DLLPRG1_DACIN_SET(0x1) | DFS_DLLPRG1_LCKWT_SET(0x0) |
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DFS_DLLPRG1_V2IGC_SET(0x5), DFS_DLLPRG1(pll));
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for (i = 0; i < dfs_nr; i++) {
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if (dfs[i][0]) {
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writel(DFS_DVPORTn_MFI_SET(dfs[i][2]) |
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DFS_DVPORTn_MFN_SET(dfs[i][1]),
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DFS_DVPORTn(pll, i));
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dfs_on |= (dfs[i][0] << i);
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}
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}
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writel(readl(DFS_CTRL(pll)) & ~DFS_CTRL_DLL_RESET,
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DFS_CTRL(pll));
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writel(readl(DFS_PORTRESET(pll)) &
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~DFS_PORTRESET_PORTRESET_SET(dfs_on),
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DFS_PORTRESET(pll));
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while ((readl(DFS_PORTSR(pll)) & dfs_on) != dfs_on) ;
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}
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entry_to_target_mode(MC_ME_MCTL_RUN0);
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return 0;
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}
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static void aux_source_clk_config(uintptr_t cgm_addr, u8 ac, u32 source)
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{
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/* select the clock source */
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writel(MC_CGM_ACn_SEL_SET(source), CGM_ACn_SC(cgm_addr, ac));
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}
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static void aux_div_clk_config(uintptr_t cgm_addr, u8 ac, u8 dc, u32 divider)
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{
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/* set the divider */
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writel(MC_CGM_ACn_DCm_DE | MC_CGM_ACn_DCm_PREDIV(divider),
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CGM_ACn_DCm(cgm_addr, ac, dc));
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}
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static void setup_sys_clocks(void)
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{
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/* set ARM PLL DFS 1 as SYSCLK */
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writel((readl(MC_ME_RUNn_MC(0)) & ~MC_ME_RUNMODE_MC_SYSCLK_MASK) |
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MC_ME_RUNMODE_MC_SYSCLK(0x2), MC_ME_RUNn_MC(0));
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entry_to_target_mode(MC_ME_MCTL_RUN0);
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/* select sysclks ARMPLL, ARMPLLDFS2, ARMPLLDFS3 */
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writel(MC_ME_RUNMODE_SEC_CC_I_SYSCLK
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(0x2,
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MC_ME_RUNMODE_SEC_CC_I_SYSCLK1_OFFSET) |
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MC_ME_RUNMODE_SEC_CC_I_SYSCLK(0x2,
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MC_ME_RUNMODE_SEC_CC_I_SYSCLK2_OFFSET)
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| MC_ME_RUNMODE_SEC_CC_I_SYSCLK(0x2,
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MC_ME_RUNMODE_SEC_CC_I_SYSCLK3_OFFSET),
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MC_ME_RUNn_SEC_CC_I(0));
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/* setup the sys clock divider for CORE_CLK (1000MHz) */
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writel(MC_CGM_SC_DCn_DE | MC_CGM_SC_DCn_PREDIV(0x0),
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CGM_SC_DCn(MC_CGM1_BASE_ADDR, 0));
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/* setup the sys clock divider for CORE2_CLK (500MHz) */
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writel(MC_CGM_SC_DCn_DE | MC_CGM_SC_DCn_PREDIV(0x1),
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CGM_SC_DCn(MC_CGM1_BASE_ADDR, 1));
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/* setup the sys clock divider for SYS3_CLK (266 MHz) */
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writel(MC_CGM_SC_DCn_DE | MC_CGM_SC_DCn_PREDIV(0x0),
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CGM_SC_DCn(MC_CGM0_BASE_ADDR, 0));
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/* setup the sys clock divider for SYS6_CLK (133 Mhz) */
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writel(MC_CGM_SC_DCn_DE | MC_CGM_SC_DCn_PREDIV(0x1),
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CGM_SC_DCn(MC_CGM0_BASE_ADDR, 1));
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entry_to_target_mode(MC_ME_MCTL_RUN0);
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}
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static void setup_aux_clocks(void)
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{
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/*
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* setup the aux clock divider for PERI_CLK
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* (source: PERIPH_PLL_PHI_0/5, PERI_CLK - 80 MHz)
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*/
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aux_source_clk_config(MC_CGM0_BASE_ADDR, 5, MC_CGM_ACn_SEL_PERPLLDIVX);
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aux_div_clk_config(MC_CGM0_BASE_ADDR, 5, 0, 4);
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/* setup the aux clock divider for LIN_CLK (40MHz) */
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aux_source_clk_config(MC_CGM0_BASE_ADDR, 3, MC_CGM_ACn_SEL_PERPLLDIVX);
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aux_div_clk_config(MC_CGM0_BASE_ADDR, 3, 0, 1);
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/* setup the aux clock divider for ENET_TIME_CLK (50MHz) */
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aux_source_clk_config(MC_CGM0_BASE_ADDR, 7, MC_CGM_ACn_SEL_ENETPLL);
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aux_div_clk_config(MC_CGM0_BASE_ADDR, 7, 1, 9);
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/* setup the aux clock divider for ENET_CLK (50MHz) */
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aux_source_clk_config(MC_CGM2_BASE_ADDR, 2, MC_CGM_ACn_SEL_ENETPLL);
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aux_div_clk_config(MC_CGM2_BASE_ADDR, 2, 0, 9);
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/* setup the aux clock divider for SDHC_CLK (50 MHz). */
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aux_source_clk_config(MC_CGM0_BASE_ADDR, 15, MC_CGM_ACn_SEL_ENETPLL);
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aux_div_clk_config(MC_CGM0_BASE_ADDR, 15, 0, 9);
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/* setup the aux clock divider for DDR_CLK (533MHz) and APEX_SYS_CLK (266MHz) */
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aux_source_clk_config(MC_CGM0_BASE_ADDR, 8, MC_CGM_ACn_SEL_DDRPLL);
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aux_div_clk_config(MC_CGM0_BASE_ADDR, 8, 0, 0);
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/* setup the aux clock divider for DDR4_CLK (133,25MHz) */
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aux_div_clk_config(MC_CGM0_BASE_ADDR, 8, 1, 3);
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entry_to_target_mode(MC_ME_MCTL_RUN0);
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}
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static void enable_modules_clock(void)
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{
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/* PIT0 */
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writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL58);
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/* PIT1 */
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writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL170);
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/* LINFLEX0 */
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writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL83);
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/* LINFLEX1 */
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writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL188);
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/* ENET */
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writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL50);
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/* SDHC */
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writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL93);
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/* IIC0 */
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writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL81);
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/* IIC1 */
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writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL184);
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/* IIC2 */
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writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL186);
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/* MMDC0 */
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writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL54);
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/* MMDC1 */
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writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL162);
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entry_to_target_mode(MC_ME_MCTL_RUN0);
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}
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void clock_init(void)
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{
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unsigned int arm_dfs[ARM_PLL_PHI1_DFS_Nr][DFS_PARAMS_Nr] = {
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{ARM_PLL_PHI1_DFS1_EN, ARM_PLL_PHI1_DFS1_MFN,
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ARM_PLL_PHI1_DFS1_MFI},
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{ARM_PLL_PHI1_DFS2_EN, ARM_PLL_PHI1_DFS2_MFN,
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ARM_PLL_PHI1_DFS2_MFI},
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{ARM_PLL_PHI1_DFS3_EN, ARM_PLL_PHI1_DFS3_MFN,
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ARM_PLL_PHI1_DFS3_MFI}
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};
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unsigned int enet_dfs[ENET_PLL_PHI1_DFS_Nr][DFS_PARAMS_Nr] = {
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{ENET_PLL_PHI1_DFS1_EN, ENET_PLL_PHI1_DFS1_MFN,
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ENET_PLL_PHI1_DFS1_MFI},
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{ENET_PLL_PHI1_DFS2_EN, ENET_PLL_PHI1_DFS2_MFN,
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ENET_PLL_PHI1_DFS2_MFI},
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{ENET_PLL_PHI1_DFS3_EN, ENET_PLL_PHI1_DFS3_MFN,
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ENET_PLL_PHI1_DFS3_MFI},
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{ENET_PLL_PHI1_DFS4_EN, ENET_PLL_PHI1_DFS4_MFN,
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ENET_PLL_PHI1_DFS4_MFI}
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};
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unsigned int ddr_dfs[DDR_PLL_PHI1_DFS_Nr][DFS_PARAMS_Nr] = {
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{DDR_PLL_PHI1_DFS1_EN, DDR_PLL_PHI1_DFS1_MFN,
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DDR_PLL_PHI1_DFS1_MFI},
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{DDR_PLL_PHI1_DFS2_EN, DDR_PLL_PHI1_DFS2_MFN,
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DDR_PLL_PHI1_DFS2_MFI},
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{DDR_PLL_PHI1_DFS3_EN, DDR_PLL_PHI1_DFS3_MFN,
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DDR_PLL_PHI1_DFS3_MFI}
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};
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writel(MC_ME_RUN_PCn_DRUN | MC_ME_RUN_PCn_RUN0 | MC_ME_RUN_PCn_RUN1 |
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MC_ME_RUN_PCn_RUN2 | MC_ME_RUN_PCn_RUN3, MC_ME_RUN_PCn(0));
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/* turn on FXOSC */
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writel(MC_ME_RUNMODE_MC_MVRON | MC_ME_RUNMODE_MC_XOSCON |
|
||
|
|
MC_ME_RUNMODE_MC_FIRCON | MC_ME_RUNMODE_MC_SYSCLK(0x1),
|
||
|
|
MC_ME_RUNn_MC(0));
|
||
|
|
|
||
|
|
entry_to_target_mode(MC_ME_MCTL_RUN0);
|
||
|
|
|
||
|
|
program_pll(ARM_PLL, XOSC_CLK_FREQ, ARM_PLL_PHI0_FREQ,
|
||
|
|
ARM_PLL_PHI1_FREQ, ARM_PLL_PHI1_DFS_Nr, arm_dfs,
|
||
|
|
ARM_PLL_PLLDV_PREDIV, ARM_PLL_PLLDV_MFD, ARM_PLL_PLLDV_MFN);
|
||
|
|
|
||
|
|
setup_sys_clocks();
|
||
|
|
|
||
|
|
program_pll(PERIPH_PLL, XOSC_CLK_FREQ, PERIPH_PLL_PHI0_FREQ,
|
||
|
|
PERIPH_PLL_PHI1_FREQ, PERIPH_PLL_PHI1_DFS_Nr, NULL,
|
||
|
|
PERIPH_PLL_PLLDV_PREDIV, PERIPH_PLL_PLLDV_MFD,
|
||
|
|
PERIPH_PLL_PLLDV_MFN);
|
||
|
|
|
||
|
|
program_pll(ENET_PLL, XOSC_CLK_FREQ, ENET_PLL_PHI0_FREQ,
|
||
|
|
ENET_PLL_PHI1_FREQ, ENET_PLL_PHI1_DFS_Nr, enet_dfs,
|
||
|
|
ENET_PLL_PLLDV_PREDIV, ENET_PLL_PLLDV_MFD,
|
||
|
|
ENET_PLL_PLLDV_MFN);
|
||
|
|
|
||
|
|
program_pll(DDR_PLL, XOSC_CLK_FREQ, DDR_PLL_PHI0_FREQ,
|
||
|
|
DDR_PLL_PHI1_FREQ, DDR_PLL_PHI1_DFS_Nr, ddr_dfs,
|
||
|
|
DDR_PLL_PLLDV_PREDIV, DDR_PLL_PLLDV_MFD, DDR_PLL_PLLDV_MFN);
|
||
|
|
|
||
|
|
program_pll(VIDEO_PLL, XOSC_CLK_FREQ, VIDEO_PLL_PHI0_FREQ,
|
||
|
|
VIDEO_PLL_PHI1_FREQ, VIDEO_PLL_PHI1_DFS_Nr, NULL,
|
||
|
|
VIDEO_PLL_PLLDV_PREDIV, VIDEO_PLL_PLLDV_MFD,
|
||
|
|
VIDEO_PLL_PLLDV_MFN);
|
||
|
|
|
||
|
|
setup_aux_clocks();
|
||
|
|
|
||
|
|
enable_modules_clock();
|
||
|
|
|
||
|
|
}
|