105 lines
2.0 KiB
C
105 lines
2.0 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2013
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* David Feng <fenghua@phytium.com.cn>
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* Sharma Bhupesh <bhupesh.sharma@freescale.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <malloc.h>
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#include <errno.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <linux/compiler.h>
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#include <dm/platform_data/serial_pl01x.h>
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#include "pcie.h"
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#include <asm/armv8/mmu.h>
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DECLARE_GLOBAL_DATA_PTR;
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static const struct pl01x_serial_platdata serial_platdata = {
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.base = V2M_UART0,
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.type = TYPE_PL011,
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.clock = CONFIG_PL011_CLOCK,
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};
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U_BOOT_DEVICE(vexpress_serials) = {
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.name = "serial_pl01x",
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.platdata = &serial_platdata,
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};
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static struct mm_region vexpress64_mem_map[] = {
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{
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.virt = 0x0UL,
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.phys = 0x0UL,
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.size = 0x80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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.virt = 0x80000000UL,
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.phys = 0x80000000UL,
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.size = 0xff80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = vexpress64_mem_map;
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/* This function gets replaced by platforms supporting PCIe.
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* The replacement function, eg. on Juno, initialises the PCIe bus.
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*/
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__weak void vexpress64_pcie_init(void)
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{
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}
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int board_init(void)
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{
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vexpress64_pcie_init();
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = PHYS_SDRAM_1_SIZE;
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return 0;
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}
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int dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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#ifdef PHYS_SDRAM_2
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gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
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gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
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#endif
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return 0;
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}
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/*
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* Board specific reset that is system reset.
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*/
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void reset_cpu(ulong addr)
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{
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}
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/*
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* Board specific ethernet initialization routine.
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*/
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int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_SMC91111
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rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
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#endif
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#ifdef CONFIG_SMC911X
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rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
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#endif
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return rc;
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}
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