39 lines
738 B
Plaintext
39 lines
738 B
Plaintext
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019 Intel Corporation <www.intel.com>
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*
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*/
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/dts-v1/;
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/ {
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description = "FIT image with FPGA bistream";
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#address-cells = <1>;
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images {
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fpga-periph-1 {
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description = "FPGA peripheral bitstream";
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data = /incbin/("../../../ghrd_10as066n2.periph.rbf");
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type = "fpga";
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arch = "arm";
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compression = "none";
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};
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fpga-core-1 {
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description = "FPGA core bitstream";
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data = /incbin/("../../../ghrd_10as066n2.core.rbf");
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type = "fpga";
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arch = "arm";
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compression = "none";
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};
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};
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configurations {
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default = "config-1";
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config-1 {
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description = "Boot with FPGA early IO release config";
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fpga = "fpga-periph-1", "fpga-core-1";
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};
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};
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};
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