82 lines
1.8 KiB
C
82 lines
1.8 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
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*/
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#include <common.h>
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#include <asm/io.h>
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#define PCI_DEV_CONFIG(segbus, dev, fn) ( \
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(((segbus) & 0xfff) << 20) | \
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(((dev) & 0x1f) << 15) | \
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(((fn) & 0x07) << 12))
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/* Platform Controller Unit */
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#define LPC_DEV 0x1f
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#define LPC_FUNC 0
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/* Enable UART */
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#define UART_CONT 0x80
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/* UART PAD definitions */
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#define UART_RXD_COMMUITY 1
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#define UART_TXD_COMMUITY 1
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#define UART_RXD_FAMILY 4
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#define UART_TXD_FAMILY 4
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#define UART_RXD_PAD 2
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#define UART_TXD_PAD 7
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#define UART_RXD_FUNC 3
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#define UART_TXD_FUNC 3
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/* IO Memory */
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#define IO_BASE_ADDRESS 0xfed80000
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static inline uint32_t gpio_pconf0(int community, int family, int pad)
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{
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return IO_BASE_ADDRESS + community * 0x8000 + 0x4400 +
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family * 0x400 + pad * 8;
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}
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static void gpio_select_func(int community, int family, int pad, int func)
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{
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uint32_t pconf0_addr = gpio_pconf0(community, family, pad);
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clrsetbits_le32(pconf0_addr, 0xf << 16, func << 16);
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}
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static void x86_pci_write_config32(int dev, unsigned int where, u32 value)
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{
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unsigned long addr;
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addr = CONFIG_PCIE_ECAM_BASE | dev | (where & ~3);
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writel(value, addr);
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}
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/* This can be called after memory-mapped PCI is working */
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int setup_internal_uart(int enable)
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{
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/* Enable or disable the legacy UART hardware */
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x86_pci_write_config32(PCI_DEV_CONFIG(0, LPC_DEV, LPC_FUNC), UART_CONT,
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enable);
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/* All done for the disable part, so just return */
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if (!enable)
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return 0;
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/*
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* Set up the pads to the UART function. This allows the signals to
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* leave the chip
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*/
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gpio_select_func(UART_RXD_COMMUITY, UART_RXD_FAMILY,
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UART_RXD_PAD, UART_RXD_FUNC);
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gpio_select_func(UART_TXD_COMMUITY, UART_TXD_FAMILY,
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UART_TXD_PAD, UART_TXD_FUNC);
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return 0;
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}
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void board_debug_uart_init(void)
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{
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setup_internal_uart(1);
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}
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