355 lines
8.0 KiB
Plaintext
355 lines
8.0 KiB
Plaintext
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/*
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* Basic platform for gdsys mpc8308 based devices
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*
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* (C) Copyright 2014
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* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
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*
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* based on mpc8308rdb
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* Copyright 2009 Freescale Semiconductor Inc.
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* Copyright 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/dts-v1/;
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#include <dt-bindings/memory/mpc83xx-sdram.h>
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/ {
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compatible = "fsl,mpc8308rdb";
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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serial0 = &serial0;
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serial1 = &serial1;
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};
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memory {
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device_type = "memory";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8308@0 {
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device_type = "cpu";
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reg = <0x0>;
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d-cache-line-size = <32>;
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i-cache-line-size = <32>;
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d-cache-size = <16384>;
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i-cache-size = <16384>;
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timebase-frequency = <0>; // from bootloader
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bus-frequency = <0>; // from bootloader
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clock-frequency = <0>; // from bootloader
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};
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};
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board_lbc: localbus@e0005000 {
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#address-cells = <2>;
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#size-cells = <1>;
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compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
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reg = <0xe0005000 0x1000>;
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interrupts = <77 0x8>;
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interrupt-parent = <&ipic>;
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};
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board_soc: immr@e0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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compatible = "fsl,mpc8308-immr", "simple-bus";
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ranges = <0 0xe0000000 0x00100000>;
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reg = <0xe0000000 0x00000200>;
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bus-frequency = <0>;
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wdt@200 {
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device_type = "watchdog";
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compatible = "mpc83xx_wdt";
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reg = <0x200 0x100>;
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};
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memory@2000 {
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#address-cells = <2>;
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#size-cells = <1>;
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compatible = "fsl,mpc83xx-mem-controller";
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reg = <0x2000 0x1000>;
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device_type = "memory";
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driver_software_override = <DSO_ENABLE>;
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p_impedance_override = <DSO_P_IMPEDANCE_NOMINAL>;
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n_impedance_override = <DSO_N_IMPEDANCE_NOMINAL>;
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odt_termination_value = <ODT_TERMINATION_150_OHM>;
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ddr_type = <DDR_TYPE_DDR2_1_8_VOLT>;
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clock_adjust = <CLOCK_ADJUST_05>;
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read_to_write = <0>;
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write_to_read = <0>;
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read_to_read = <0>;
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write_to_write = <0>;
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active_powerdown_exit = <2>;
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precharge_powerdown_exit = <6>;
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odt_powerdown_exit = <8>;
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mode_reg_set_cycle = <2>;
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precharge_to_activate = <2>;
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activate_to_precharge = <6>;
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activate_to_readwrite = <2>;
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mcas_latency = <CASLAT_40>;
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refresh_recovery = <17>;
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last_data_to_precharge = <2>;
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activate_to_activate = <2>;
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last_write_data_to_read = <2>;
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additive_latency = <0>;
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mcas_to_preamble_override = <READ_LAT_PLUS_1_2>;
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write_latency = <3>;
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read_to_precharge = <2>;
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write_cmd_to_write_data = <CLOCK_DELAY_1_2>;
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minimum_cke_pulse_width = <3>;
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four_activates_window = <5>;
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self_refresh = <SREN_ENABLE>;
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sdram_type = <TYPE_DDR2>;
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databus_width = <DATA_BUS_WIDTH_32>;
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force_self_refresh = <MODE_NORMAL>;
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dll_reset = <DLL_RESET_ENABLE>;
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dqs_config = <DQS_TRUE>;
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odt_config = <ODT_ASSERT_READS>;
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posted_refreshes = <1>;
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refresh_interval = <2084>;
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precharge_interval = <256>;
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sdmode = <0x0242>;
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esdmode = <0x0440>;
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ram@0 {
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reg = <0x0 0x0 0x8000000>;
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compatible = "nanya,nt5tu64m16hg";
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odt_rd_cfg = <ODT_RD_NEVER>;
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odt_wr_cfg = <ODT_WR_ONLY_CURRENT>;
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bank_bits = <3>;
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row_bits = <13>;
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col_bits = <10>;
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};
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};
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IIC:i2c@3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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compatible = "fsl-i2c";
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reg = <0x3000 0x100>;
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interrupts = <14 0x8>;
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interrupt-parent = <&ipic>;
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dfsrr;
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};
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IIC2: i2c@3100 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl-i2c";
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reg = <0x3100 0x100>;
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interrupts = <15 0x8>;
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interrupt-parent = <&ipic>;
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dfsrr;
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status = "disabled";
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};
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SPI:spi@7000 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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compatible = "fsl,spi";
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reg = <0x7000 0x1000>;
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interrupts = <16 0x8>;
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interrupt-parent = <&ipic>;
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mode = "cpu";
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};
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sdhc@2e000 {
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compatible = "fsl,esdhc", "fsl,mpc8308-esdhc";
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reg = <0x2e000 0x1000>;
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interrupts = <42 0x8>;
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interrupt-parent = <&ipic>;
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sdhci,auto-cmd12;
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/* Filled in by U-Boot */
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clock-frequency = <0>;
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};
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serial0: serial@4500 {
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cell-index = <0>;
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device_type = "serial";
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compatible = "fsl,ns16550", "ns16550";
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reg = <0x4500 0x100>;
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clock-frequency = <133333333>;
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interrupts = <9 0x8>;
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interrupt-parent = <&ipic>;
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};
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serial1: serial@4600 {
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cell-index = <1>;
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device_type = "serial";
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compatible = "fsl,ns16550", "ns16550";
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reg = <0x4600 0x100>;
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clock-frequency = <133333333>;
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interrupts = <10 0x8>;
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interrupt-parent = <&ipic>;
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};
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gpio0: gpio@c00 {
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#gpio-cells = <2>;
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device_type = "gpio";
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compatible = "fsl,mpc8308-gpio", "fsl,mpc8349-gpio";
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reg = <0xc00 0x18>;
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interrupts = <74 0x8>;
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interrupt-parent = <&ipic>;
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gpio-controller;
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};
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/* IPIC
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* interrupts cell = <intr #, sense>
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* sense values match linux IORESOURCE_IRQ_* defines:
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* sense == 8: Level, low assertion
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* sense == 2: Edge, high-to-low change
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*/
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ipic: interrupt-controller@700 {
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compatible = "fsl,ipic";
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <0x700 0x100>;
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device_type = "ipic";
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};
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ipic-msi@7c0 {
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compatible = "fsl,ipic-msi";
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reg = <0x7c0 0x40>;
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msi-available-ranges = <0x0 0x100>;
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interrupts = < 0x43 0x8
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0x4 0x8
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0x51 0x8
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0x52 0x8
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0x56 0x8
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0x57 0x8
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0x58 0x8
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0x59 0x8 >;
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interrupt-parent = < &ipic >;
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};
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dma@2c000 {
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compatible = "fsl,mpc8308-dma", "fsl,mpc5121-dma";
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reg = <0x2c000 0x1800>;
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interrupts = <3 0x8
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94 0x8>;
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interrupt-parent = < &ipic >;
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};
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enet0: ethernet@24000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x24000 0x1000>;
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cell-index = <0>;
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device_type = "network";
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model = "eTSEC";
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compatible = "gianfar", "fsl,tsec";
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reg = <0x24000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <32 0x8 33 0x8 34 0x8>;
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interrupt-parent = <&ipic>;
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tbi-handle = < &tbi0 >;
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phy-handle = < &phy1 >;
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fsl,magic-packet;
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mdio@520 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,gianfar-mdio";
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reg = <0x520 0x20>;
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phy1: ethernet-phy@1 {
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reg = <0x1>;
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};
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phy2: ethernet-phy@0 {
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reg = <0x0>;
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device_type = "ethernet-phy";
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};
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tbi0: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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};
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enet1: ethernet@25000 {
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#address-cells = <1>;
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#size-cells = <1>;
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cell-index = <1>;
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device_type = "network";
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model = "eTSEC";
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compatible = "gianfar", "fsl,tsec";
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reg = <0x25000 0x1000>;
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ranges = <0x0 0x25000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <35 0x8 36 0x8 37 0x8>;
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interrupt-parent = <&ipic>;
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phy-handle = < &phy2 >;
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status = "disabled";
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mdio@520 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,gianfar-tbi";
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reg = <0x520 0x20>;
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tbi1: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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};
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};
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pci0: pcie@e0009000 {
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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device_type = "pci";
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compatible = "fsl,mpc8308-pcie", "fsl,mpc8314-pcie";
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reg = <0xe0009000 0x00001000
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0xb0000000 0x01000000>;
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ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
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0x01000000 0 0x00000000 0xb1000000 0 0x00800000>;
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bus-range = <0 0>;
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interrupt-map-mask = <0xf800 0 0 7>;
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interrupt-map = <0 0 0 1 &ipic 1 8
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0 0 0 2 &ipic 1 8
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0 0 0 3 &ipic 1 8
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0 0 0 4 &ipic 1 8>;
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interrupts = <0x1 0x8>;
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interrupt-parent = <&ipic>;
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clock-frequency = <0>;
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pcie@0 {
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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reg = <0 0 0 0 0>;
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ranges = <0x02000000 0 0xa0000000
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0x02000000 0 0xa0000000
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0 0x10000000
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0x01000000 0 0x00000000
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0x01000000 0 0x00000000
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0 0x00800000>;
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};
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};
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};
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