74 lines
1.6 KiB
C
74 lines
1.6 KiB
C
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2018 Microsemi Corporation
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*/
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#include <common.h>
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#include <asm/io.h>
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int mscc_phy_rd_wr(u8 read,
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u32 miimdev,
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u8 miim_addr,
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u8 addr,
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u16 *value)
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{
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u32 data;
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int i;
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/* Command part */
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data = (read ? MSCC_F_MII_CMD_MIIM_CMD_OPR_FIELD(2) : /* Read */
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MSCC_F_MII_CMD_MIIM_CMD_OPR_FIELD(1) | /* Write */
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MSCC_F_MII_CMD_MIIM_CMD_WRDATA(*value)); /* value */
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/* Addressing part */
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data |=
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MSCC_F_MII_CMD_MIIM_CMD_VLD(1) | /* Valid command */
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MSCC_F_MII_CMD_MIIM_CMD_REGAD(addr) | /* Reg addr */
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MSCC_F_MII_CMD_MIIM_CMD_PHYAD(miim_addr); /* Miim addr */
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/* Enqueue MIIM operation to be executed */
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writel(data, BASE_DEVCPU_GCB + MIIM_MII_CMD(miimdev));
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/* Wait for MIIM operation to finish */
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i = 0;
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do {
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if (i++ > 100) {
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debug("Miim timeout");
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return -1;
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}
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data = readl(BASE_DEVCPU_GCB + MIIM_MII_STATUS(miimdev));
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debug("Read status miim(%d): 0x%08x\n", miimdev, data);
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} while (data & MSCC_F_MII_STATUS_MIIM_STAT_BUSY(1));
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if (read) {
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data = readl(BASE_DEVCPU_GCB + MIIM_MII_DATA(miimdev));
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if (data & MSCC_M_MII_DATA_MIIM_DATA_SUCCESS) {
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debug("Read(%d, %d) returned 0x%08x\n",
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miim_addr, addr, data);
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return -1;
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}
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*value = MSCC_X_MII_DATA_MIIM_DATA_RDDATA(data);
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}
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return 0;
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}
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int mscc_phy_rd(u32 miimdev,
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u8 miim_addr,
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u8 addr,
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u16 *value)
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{
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if (mscc_phy_rd_wr(1, miimdev, miim_addr, addr, value) == 0)
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return 0;
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debug("Read(%d, %d) returned error\n", miim_addr, addr);
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return -1;
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}
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int mscc_phy_wr(u32 miimdev,
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u8 miim_addr,
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u8 addr,
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u16 value)
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{
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return mscc_phy_rd_wr(0, miimdev, miim_addr, addr, &value);
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}
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