56 lines
1.6 KiB
C
56 lines
1.6 KiB
C
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/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2018 Microsemi Corporation
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*/
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#ifndef __ASM_MACH_TLB_H
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#define __ASM_MACH_TLB_H
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#include <asm/mipsregs.h>
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#include <mach/common.h>
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#include <linux/sizes.h>
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#define TLB_HI_MASK 0xffffe000
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#define TLB_LO_MASK 0x3fffffff /* Masks off Fill bits */
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#define TLB_LO_SHIFT 6 /* PFN Start bit */
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#define PAGEMASK_SHIFT 13
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#define MMU_PAGE_CACHED (3 << 3) /* C(5:3) Cache Coherency Attributes */
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#define MMU_PAGE_UNCACHED (2 << 3) /* C(5:3) Cache Coherency Attributes */
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#define MMU_PAGE_DIRTY BIT(2) /* = Writeable */
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#define MMU_PAGE_VALID BIT(1)
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#define MMU_PAGE_GLOBAL BIT(0)
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#define MMU_REGIO_RO_C (MMU_PAGE_CACHED | MMU_PAGE_VALID | MMU_PAGE_GLOBAL)
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#define MMU_REGIO_RO (MMU_PAGE_UNCACHED | MMU_PAGE_VALID | MMU_PAGE_GLOBAL)
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#define MMU_REGIO_RW (MMU_PAGE_DIRTY | MMU_REGIO_RO)
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#define MMU_REGIO_INVAL (MMU_PAGE_GLOBAL)
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#define TLB_COUNT_MASK GENMASK(5, 0)
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#define TLB_COUNT_OFF 25
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static inline u32 get_tlb_count(void)
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{
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register u32 config1;
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config1 = read_c0_config1();
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config1 >>= TLB_COUNT_OFF;
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config1 &= TLB_COUNT_MASK;
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return 1 + config1;
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}
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static inline void create_tlb(int index, u32 offset, u32 size, u32 tlb_attrib1,
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u32 tlb_attrib2)
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{
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register u32 tlb_mask, tlb_lo0, tlb_lo1;
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tlb_mask = ((size >> 12) - 1) << PAGEMASK_SHIFT;
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tlb_lo0 = tlb_attrib1 | (offset >> TLB_LO_SHIFT);
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tlb_lo1 = tlb_attrib2 | ((offset + size) >> TLB_LO_SHIFT);
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write_one_tlb(index, tlb_mask, offset & TLB_HI_MASK,
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tlb_lo0 & TLB_LO_MASK, tlb_lo1 & TLB_LO_MASK);
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}
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#endif /* __ASM_MACH_TLB_H */
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