475 lines
8.7 KiB
Plaintext
475 lines
8.7 KiB
Plaintext
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2018 Microsemi Corporation
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*/
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/dts-v1/;
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#include "mscc,jr2.dtsi"
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#include <dt-bindings/mscc/jr2_data.h>
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/ {
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model = "Jaguar2 Cu48 PCB111 Reference Board";
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compatible = "mscc,jr2-pcb111", "mscc,jr2";
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aliases {
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spi0 = &spi0;
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serial0 = &uart0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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gpio-leds {
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compatible = "gpio-leds";
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status_green {
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label = "pcb111:green:status";
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gpios = <&gpio 12 0>;
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default-state = "on";
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};
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status_red {
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label = "pcb111:red:status";
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gpios = <&gpio 13 0>;
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default-state = "off";
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};
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};
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};
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&uart0 {
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status = "okay";
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};
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&spi0 {
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status = "okay";
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spi-flash@0 {
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compatible = "jedec,spi-nor";
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spi-max-frequency = <18000000>; /* input clock */
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reg = <0>; /* CS0 */
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};
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};
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&gpio {
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/* SPIO only use DO, CLK, no inputs */
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sgpio1_pins: sgpio1-pins {
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pins = "GPIO_4", "GPIO_5";
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function = "sg1";
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};
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};
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&sgpio {
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status = "okay";
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sgpio-ports = <0xffffffff>;
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};
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&sgpio1 {
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status = "okay";
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sgpio-ports = <0x001effff>;
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};
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&sgpio2 {
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status = "okay";
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sgpio-ports = <0xff000000>;
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gpio-ranges = <&sgpio2 0 0 96>;
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};
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&mdio1 {
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status = "okay";
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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phy1: ethernet-phy@1 {
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reg = <1>;
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};
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phy2: ethernet-phy@2 {
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reg = <2>;
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};
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phy3: ethernet-phy@3 {
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reg = <3>;
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};
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phy4: ethernet-phy@4 {
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reg = <4>;
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};
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phy5: ethernet-phy@5 {
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reg = <5>;
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};
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phy6: ethernet-phy@6 {
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reg = <6>;
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};
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phy7: ethernet-phy@7 {
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reg = <7>;
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};
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phy8: ethernet-phy@8 {
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reg = <8>;
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};
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phy9: ethernet-phy@9 {
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reg = <9>;
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};
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phy10: ethernet-phy@10 {
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reg = <10>;
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};
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phy11: ethernet-phy@11 {
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reg = <11>;
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};
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phy12: ethernet-phy@12 {
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reg = <12>;
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};
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phy13: ethernet-phy@13 {
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reg = <13>;
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};
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phy14: ethernet-phy@14 {
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reg = <14>;
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};
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phy15: ethernet-phy@15 {
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reg = <15>;
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};
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phy16: ethernet-phy@16 {
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reg = <16>;
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};
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phy17: ethernet-phy@17 {
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reg = <17>;
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};
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phy18: ethernet-phy@18 {
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reg = <18>;
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};
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phy19: ethernet-phy@19 {
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reg = <19>;
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};
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phy20: ethernet-phy@20 {
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reg = <20>;
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};
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phy21: ethernet-phy@21 {
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reg = <21>;
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};
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phy22: ethernet-phy@22 {
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reg = <22>;
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};
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phy23: ethernet-phy@23 {
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reg = <23>;
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};
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};
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&mdio2 {
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status = "okay";
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phy24: ethernet-phy@24 {
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reg = <0>;
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};
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phy25: ethernet-phy@25 {
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reg = <1>;
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};
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phy26: ethernet-phy@26 {
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reg = <2>;
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};
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phy27: ethernet-phy@27 {
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reg = <3>;
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};
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phy28: ethernet-phy@28 {
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reg = <4>;
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};
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phy29: ethernet-phy@29 {
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reg = <5>;
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};
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phy30: ethernet-phy@30 {
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reg = <6>;
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};
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phy31: ethernet-phy@31 {
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reg = <7>;
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};
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phy32: ethernet-phy@32 {
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reg = <8>;
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};
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phy33: ethernet-phy@33 {
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reg = <9>;
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};
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phy34: ethernet-phy@34 {
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reg = <10>;
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};
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phy35: ethernet-phy@35 {
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reg = <11>;
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};
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phy36: ethernet-phy@36 {
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reg = <12>;
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};
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phy37: ethernet-phy@37 {
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reg = <13>;
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};
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phy38: ethernet-phy@38 {
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reg = <14>;
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};
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phy39: ethernet-phy@39 {
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reg = <15>;
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};
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phy40: ethernet-phy@40 {
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reg = <16>;
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};
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phy41: ethernet-phy@41 {
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reg = <17>;
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};
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phy42: ethernet-phy@42 {
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reg = <18>;
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};
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phy43: ethernet-phy@43 {
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reg = <19>;
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};
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phy44: ethernet-phy@44 {
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reg = <20>;
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};
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phy45: ethernet-phy@45 {
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reg = <21>;
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};
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phy46: ethernet-phy@46 {
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reg = <22>;
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};
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phy47: ethernet-phy@47 {
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reg = <23>;
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};
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};
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&switch {
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ethernet-ports {
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port0: port@0 {
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reg = <0>;
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phy-handle = <&phy0>;
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phys = <&serdes_hsio 0 SERDES6G(4) PHY_MODE_QSGMII>;
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};
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port1: port@1 {
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reg = <1>;
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phy-handle = <&phy1>;
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phys = <&serdes_hsio 1 0xff PHY_MODE_QSGMII>;
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};
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port2: port@2 {
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reg = <2>;
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phy-handle = <&phy2>;
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phys = <&serdes_hsio 2 0xff PHY_MODE_QSGMII>;
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};
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port3: port@3 {
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reg = <3>;
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phy-handle = <&phy3>;
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phys = <&serdes_hsio 3 0xff PHY_MODE_QSGMII>;
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};
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port4: port@4 {
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reg = <4>;
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phy-handle = <&phy4>;
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phys = <&serdes_hsio 4 SERDES6G(5) PHY_MODE_QSGMII>;
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};
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port5: port@5 {
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reg = <5>;
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phy-handle = <&phy5>;
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phys = <&serdes_hsio 5 0xff PHY_MODE_QSGMII>;
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};
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port6: port@6 {
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reg = <6>;
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phy-handle = <&phy6>;
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phys = <&serdes_hsio 6 0xff PHY_MODE_QSGMII>;
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};
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port7: port@7 {
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reg = <7>;
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phy-handle = <&phy7>;
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phys = <&serdes_hsio 7 0xff PHY_MODE_QSGMII>;
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};
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port8: port@8 {
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reg = <8>;
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phy-handle = <&phy8>;
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phys = <&serdes_hsio 8 SERDES6G(6) PHY_MODE_QSGMII>;
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};
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port9: port@9 {
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reg = <9>;
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phy-handle = <&phy9>;
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phys = <&serdes_hsio 9 0xff PHY_MODE_QSGMII>;
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};
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port10: port@10 {
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reg = <10>;
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phy-handle = <&phy10>;
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phys = <&serdes_hsio 10 0xff PHY_MODE_QSGMII>;
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};
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port11: port@11 {
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reg = <11>;
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phy-handle = <&phy11>;
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phys = <&serdes_hsio 11 0xff PHY_MODE_QSGMII>;
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};
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port12: port@12 {
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reg = <12>;
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phy-handle = <&phy12>;
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phys = <&serdes_hsio 12 SERDES6G(7) PHY_MODE_QSGMII>;
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};
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port13: port@13 {
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reg = <13>;
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phy-handle = <&phy13>;
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phys = <&serdes_hsio 13 0xff PHY_MODE_QSGMII>;
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};
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port14: port@14 {
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reg = <14>;
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phy-handle = <&phy14>;
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phys = <&serdes_hsio 14 0xff PHY_MODE_QSGMII>;
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};
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port15: port@15 {
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reg = <15>;
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phy-handle = <&phy15>;
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phys = <&serdes_hsio 15 0xff PHY_MODE_QSGMII>;
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};
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port16: port@16 {
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reg = <16>;
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phy-handle = <&phy16>;
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phys = <&serdes_hsio 16 SERDES6G(8) PHY_MODE_QSGMII>;
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};
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port17: port@17 {
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reg = <17>;
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phy-handle = <&phy17>;
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phys = <&serdes_hsio 17 0xff PHY_MODE_QSGMII>;
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};
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port18: port@18 {
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reg = <18>;
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phy-handle = <&phy18>;
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phys = <&serdes_hsio 18 0xff PHY_MODE_QSGMII>;
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};
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port19: port@19 {
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reg = <19>;
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phy-handle = <&phy19>;
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phys = <&serdes_hsio 19 0xff PHY_MODE_QSGMII>;
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};
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port20: port@20 {
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reg = <20>;
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phy-handle = <&phy20>;
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phys = <&serdes_hsio 20 SERDES6G(9) PHY_MODE_QSGMII>;
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};
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port21: port@21 {
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reg = <21>;
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phy-handle = <&phy21>;
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phys = <&serdes_hsio 21 0xff PHY_MODE_QSGMII>;
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};
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port22: port@22 {
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reg = <22>;
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phy-handle = <&phy22>;
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phys = <&serdes_hsio 22 0xff PHY_MODE_QSGMII>;
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};
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port23: port@23 {
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reg = <23>;
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phy-handle = <&phy23>;
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phys = <&serdes_hsio 23 0xff PHY_MODE_QSGMII>;
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};
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port24: port@24 {
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reg = <24>;
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phy-handle = <&phy24>;
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phys = <&serdes_hsio 24 SERDES6G(10) PHY_MODE_QSGMII>;
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};
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port25: port@25 {
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reg = <25>;
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phy-handle = <&phy25>;
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phys = <&serdes_hsio 25 0xff PHY_MODE_QSGMII>;
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};
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port26: port@26 {
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reg = <26>;
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phy-handle = <&phy26>;
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phys = <&serdes_hsio 26 0xff PHY_MODE_QSGMII>;
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};
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port27: port@27 {
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reg = <27>;
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phy-handle = <&phy27>;
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phys = <&serdes_hsio 27 0xff PHY_MODE_QSGMII>;
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};
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port28: port@28 {
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reg = <28>;
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phy-handle = <&phy28>;
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phys = <&serdes_hsio 28 SERDES6G(11) PHY_MODE_QSGMII>;
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};
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port29: port@29 {
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reg = <29>;
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phy-handle = <&phy29>;
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phys = <&serdes_hsio 29 0xff PHY_MODE_QSGMII>;
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};
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port30: port@30 {
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reg = <30>;
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phy-handle = <&phy30>;
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phys = <&serdes_hsio 30 0xff PHY_MODE_QSGMII>;
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};
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port31: port@31 {
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reg = <31>;
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phy-handle = <&phy31>;
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phys = <&serdes_hsio 31 0xff PHY_MODE_QSGMII>;
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};
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port32: port@32 {
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reg = <32>;
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phy-handle = <&phy32>;
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phys = <&serdes_hsio 32 SERDES6G(12) PHY_MODE_QSGMII>;
|
||
|
|
};
|
||
|
|
port33: port@33 {
|
||
|
|
reg = <33>;
|
||
|
|
phy-handle = <&phy33>;
|
||
|
|
phys = <&serdes_hsio 33 0xff PHY_MODE_QSGMII>;
|
||
|
|
};
|
||
|
|
port34: port@34 {
|
||
|
|
reg = <34>;
|
||
|
|
phy-handle = <&phy34>;
|
||
|
|
phys = <&serdes_hsio 34 0xff PHY_MODE_QSGMII>;
|
||
|
|
};
|
||
|
|
port35: port@35 {
|
||
|
|
reg = <35>;
|
||
|
|
phy-handle = <&phy35>;
|
||
|
|
phys = <&serdes_hsio 35 0xff PHY_MODE_QSGMII>;
|
||
|
|
};
|
||
|
|
port36: port@36 {
|
||
|
|
reg = <36>;
|
||
|
|
phy-handle = <&phy36>;
|
||
|
|
phys = <&serdes_hsio 36 SERDES6G(13) PHY_MODE_QSGMII>;
|
||
|
|
};
|
||
|
|
port37: port@37 {
|
||
|
|
reg = <37>;
|
||
|
|
phy-handle = <&phy37>;
|
||
|
|
phys = <&serdes_hsio 37 0xff PHY_MODE_QSGMII>;
|
||
|
|
};
|
||
|
|
port38: port@38 {
|
||
|
|
reg = <38>;
|
||
|
|
phy-handle = <&phy38>;
|
||
|
|
phys = <&serdes_hsio 38 0xff PHY_MODE_QSGMII>;
|
||
|
|
};
|
||
|
|
port39: port@39 {
|
||
|
|
reg = <39>;
|
||
|
|
phy-handle = <&phy39>;
|
||
|
|
phys = <&serdes_hsio 39 0xff PHY_MODE_QSGMII>;
|
||
|
|
};
|
||
|
|
port40: port@40 {
|
||
|
|
reg = <40>;
|
||
|
|
phy-handle = <&phy40>;
|
||
|
|
phys = <&serdes_hsio 40 SERDES6G(14) PHY_MODE_QSGMII>;
|
||
|
|
};
|
||
|
|
port41: port@41 {
|
||
|
|
reg = <41>;
|
||
|
|
phy-handle = <&phy41>;
|
||
|
|
phys = <&serdes_hsio 41 0xff PHY_MODE_QSGMII>;
|
||
|
|
};
|
||
|
|
port42: port@42 {
|
||
|
|
reg = <42>;
|
||
|
|
phy-handle = <&phy42>;
|
||
|
|
phys = <&serdes_hsio 42 0xff PHY_MODE_QSGMII>;
|
||
|
|
};
|
||
|
|
port43: port@43 {
|
||
|
|
reg = <43>;
|
||
|
|
phy-handle = <&phy43>;
|
||
|
|
phys = <&serdes_hsio 43 0xff PHY_MODE_QSGMII>;
|
||
|
|
};
|
||
|
|
port44: port@44 {
|
||
|
|
reg = <44>;
|
||
|
|
phy-handle = <&phy44>;
|
||
|
|
phys = <&serdes_hsio 44 SERDES6G(15) PHY_MODE_QSGMII>;
|
||
|
|
};
|
||
|
|
port45: port@45 {
|
||
|
|
reg = <45>;
|
||
|
|
phy-handle = <&phy45>;
|
||
|
|
phys = <&serdes_hsio 45 0xff PHY_MODE_QSGMII>;
|
||
|
|
};
|
||
|
|
port46: port@46 {
|
||
|
|
reg = <46>;
|
||
|
|
phy-handle = <&phy46>;
|
||
|
|
phys = <&serdes_hsio 46 0xff PHY_MODE_QSGMII>;
|
||
|
|
};
|
||
|
|
port47: port@47 {
|
||
|
|
reg = <47>;
|
||
|
|
phy-handle = <&phy47>;
|
||
|
|
phys = <&serdes_hsio 47 0xff PHY_MODE_QSGMII>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|