495 lines
12 KiB
Plaintext
495 lines
12 KiB
Plaintext
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menu "MIPS architecture"
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depends on MIPS
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config SYS_ARCH
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default "mips"
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config SYS_CPU
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default "mips32" if CPU_MIPS32
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default "mips64" if CPU_MIPS64
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choice
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prompt "Target select"
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optional
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config TARGET_QEMU_MIPS
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bool "Support qemu-mips"
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select ROM_EXCEPTION_VECTORS
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select SUPPORTS_BIG_ENDIAN
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select SUPPORTS_CPU_MIPS32_R1
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select SUPPORTS_CPU_MIPS32_R2
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select SUPPORTS_CPU_MIPS64_R1
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select SUPPORTS_CPU_MIPS64_R2
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select SUPPORTS_LITTLE_ENDIAN
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config TARGET_MALTA
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bool "Support malta"
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select DM
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select DM_SERIAL
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select DYNAMIC_IO_PORT_BASE
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select MIPS_CM
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select MIPS_INSERT_BOOT_CONFIG
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select MIPS_L1_CACHE_SHIFT_6
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select MIPS_L2_CACHE
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select OF_CONTROL
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select OF_ISA_BUS
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select ROM_EXCEPTION_VECTORS
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select SUPPORTS_BIG_ENDIAN
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select SUPPORTS_CPU_MIPS32_R1
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select SUPPORTS_CPU_MIPS32_R2
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select SUPPORTS_CPU_MIPS32_R6
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select SUPPORTS_CPU_MIPS64_R1
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select SUPPORTS_CPU_MIPS64_R2
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select SUPPORTS_CPU_MIPS64_R6
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select SUPPORTS_LITTLE_ENDIAN
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select SWAP_IO_SPACE
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imply CMD_DM
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config TARGET_VCT
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bool "Support vct"
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select ROM_EXCEPTION_VECTORS
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select SUPPORTS_BIG_ENDIAN
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select SUPPORTS_CPU_MIPS32_R1
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select SUPPORTS_CPU_MIPS32_R2
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select SYS_MIPS_CACHE_INIT_RAM_LOAD
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config ARCH_ATH79
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bool "Support QCA/Atheros ath79"
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select DM
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select OF_CONTROL
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imply CMD_DM
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config ARCH_MSCC
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bool "Support MSCC VCore-III"
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select OF_CONTROL
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select DM
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config ARCH_BMIPS
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bool "Support BMIPS SoCs"
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select CLK
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select CPU
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select DM
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select OF_CONTROL
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select RAM
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select SYSRESET
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imply CMD_DM
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config ARCH_MTMIPS
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bool "Support MediaTek MIPS platforms"
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select CLK
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imply CMD_DM
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select DISPLAY_CPUINFO
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select DM
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imply DM_ETH
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imply DM_GPIO
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select DM_RESET
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select DM_SERIAL
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select PINCTRL
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select PINMUX
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select PINCONF
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select RESET_MTMIPS
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imply DM_SPI
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imply DM_SPI_FLASH
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select LAST_STAGE_INIT
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select MIPS_TUNE_24KC
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select OF_CONTROL
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select ROM_EXCEPTION_VECTORS
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select SUPPORTS_CPU_MIPS32_R1
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select SUPPORTS_CPU_MIPS32_R2
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select SUPPORTS_LITTLE_ENDIAN
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select SYSRESET
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config ARCH_JZ47XX
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bool "Support Ingenic JZ47xx"
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select SUPPORT_SPL
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select OF_CONTROL
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select DM
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config MACH_PIC32
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bool "Support Microchip PIC32"
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select DM
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select OF_CONTROL
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imply CMD_DM
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config TARGET_BOSTON
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bool "Support Boston"
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select DM
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select DM_SERIAL
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select MIPS_CM
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select MIPS_L1_CACHE_SHIFT_6
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select MIPS_L2_CACHE
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select OF_BOARD_SETUP
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select OF_CONTROL
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select ROM_EXCEPTION_VECTORS
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select SUPPORTS_BIG_ENDIAN
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select SUPPORTS_CPU_MIPS32_R1
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select SUPPORTS_CPU_MIPS32_R2
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select SUPPORTS_CPU_MIPS32_R6
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select SUPPORTS_CPU_MIPS64_R1
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select SUPPORTS_CPU_MIPS64_R2
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select SUPPORTS_CPU_MIPS64_R6
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select SUPPORTS_LITTLE_ENDIAN
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imply CMD_DM
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config TARGET_XILFPGA
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bool "Support Imagination Xilfpga"
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select DM
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select DM_ETH
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select DM_GPIO
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select DM_SERIAL
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select MIPS_L1_CACHE_SHIFT_4
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select OF_CONTROL
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select ROM_EXCEPTION_VECTORS
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select SUPPORTS_CPU_MIPS32_R1
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select SUPPORTS_CPU_MIPS32_R2
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select SUPPORTS_LITTLE_ENDIAN
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imply CMD_DM
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help
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This supports IMGTEC MIPSfpga platform
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endchoice
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source "board/imgtec/boston/Kconfig"
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source "board/imgtec/malta/Kconfig"
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source "board/imgtec/xilfpga/Kconfig"
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source "board/qemu-mips/Kconfig"
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source "arch/mips/mach-ath79/Kconfig"
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source "arch/mips/mach-mscc/Kconfig"
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source "arch/mips/mach-bmips/Kconfig"
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source "arch/mips/mach-jz47xx/Kconfig"
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source "arch/mips/mach-pic32/Kconfig"
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source "arch/mips/mach-mtmips/Kconfig"
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if MIPS
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choice
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prompt "Endianness selection"
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help
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Some MIPS boards can be configured for either little or big endian
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byte order. These modes require different U-Boot images. In general there
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is one preferred byteorder for a particular system but some systems are
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just as commonly used in the one or the other endianness.
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config SYS_BIG_ENDIAN
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bool "Big endian"
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depends on SUPPORTS_BIG_ENDIAN
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config SYS_LITTLE_ENDIAN
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bool "Little endian"
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depends on SUPPORTS_LITTLE_ENDIAN
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endchoice
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choice
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prompt "CPU selection"
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default CPU_MIPS32_R2
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config CPU_MIPS32_R1
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bool "MIPS32 Release 1"
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depends on SUPPORTS_CPU_MIPS32_R1
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select 32BIT
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help
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Choose this option to build an U-Boot for release 1 through 5 of the
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MIPS32 architecture.
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config CPU_MIPS32_R2
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bool "MIPS32 Release 2"
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depends on SUPPORTS_CPU_MIPS32_R2
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select 32BIT
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help
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Choose this option to build an U-Boot for release 2 through 5 of the
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MIPS32 architecture.
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config CPU_MIPS32_R6
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bool "MIPS32 Release 6"
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depends on SUPPORTS_CPU_MIPS32_R6
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select 32BIT
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help
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Choose this option to build an U-Boot for release 6 or later of the
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MIPS32 architecture.
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config CPU_MIPS64_R1
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bool "MIPS64 Release 1"
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depends on SUPPORTS_CPU_MIPS64_R1
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select 64BIT
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help
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Choose this option to build a kernel for release 1 through 5 of the
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MIPS64 architecture.
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config CPU_MIPS64_R2
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bool "MIPS64 Release 2"
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depends on SUPPORTS_CPU_MIPS64_R2
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select 64BIT
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help
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Choose this option to build a kernel for release 2 through 5 of the
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MIPS64 architecture.
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config CPU_MIPS64_R6
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bool "MIPS64 Release 6"
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depends on SUPPORTS_CPU_MIPS64_R6
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select 64BIT
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help
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Choose this option to build a kernel for release 6 or later of the
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MIPS64 architecture.
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endchoice
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menu "General setup"
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config ROM_EXCEPTION_VECTORS
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bool "Build U-Boot image with exception vectors"
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help
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Enable this to include exception vectors in the U-Boot image. This is
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required if the U-Boot entry point is equal to the address of the
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CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu,
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U-Boot booted from parallel NOR flash).
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Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL).
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In that case the image size will be reduced by 0x500 bytes.
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config MIPS_CM_BASE
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hex "MIPS CM GCR Base Address"
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depends on MIPS_CM
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default 0x16100000 if TARGET_BOSTON
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default 0x1fbf8000
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help
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The physical base address at which to map the MIPS Coherence Manager
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Global Configuration Registers (GCRs). This should be set such that
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the GCRs occupy a region of the physical address space which is
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otherwise unused, or at minimum that software doesn't need to access.
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config MIPS_CACHE_INDEX_BASE
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hex "Index base address for cache initialisation"
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default 0x80000000 if CPU_MIPS32
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default 0xffffffff80000000 if CPU_MIPS64
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help
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This is the base address for a memory block, which is used for
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initialising the cache lines. This is also the base address of a memory
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block which is used for loading and filling cache lines when
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SYS_MIPS_CACHE_INIT_RAM_LOAD is selected.
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Normally this is CKSEG0. If the MIPS system needs to move this block
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to some SRAM or ScratchPad RAM, adapt this option accordingly.
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config MIPS_RELOCATION_TABLE_SIZE
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hex "Relocation table size"
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range 0x100 0x10000
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default "0x8000"
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---help---
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A table of relocation data will be appended to the U-Boot binary
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and parsed in relocate_code() to fix up all offsets in the relocated
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U-Boot.
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This option allows the amount of space reserved for the table to be
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adjusted in a range from 256 up to 64k. The default is 32k and should
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be ok in most cases. Reduce this value to shrink the size of U-Boot
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binary.
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The build will fail and a valid size suggested if this is too small.
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If unsure, leave at the default value.
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endmenu
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menu "OS boot interface"
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config MIPS_BOOT_CMDLINE_LEGACY
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bool "Hand over legacy command line to Linux kernel"
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default y
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help
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Enable this option if you want U-Boot to hand over the Yamon-style
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command line to the kernel. All bootargs will be prepared as argc/argv
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compatible list. The argument count (argc) is stored in register $a0.
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The address of the argument list (argv) is stored in register $a1.
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config MIPS_BOOT_ENV_LEGACY
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bool "Hand over legacy environment to Linux kernel"
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default y
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help
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Enable this option if you want U-Boot to hand over the Yamon-style
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environment to the kernel. Information like memory size, initrd
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address and size will be prepared as zero-terminated key/value list.
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The address of the environment is stored in register $a2.
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config MIPS_BOOT_FDT
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bool "Hand over a flattened device tree to Linux kernel"
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default n
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help
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Enable this option if you want U-Boot to hand over a flattened
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device tree to the kernel. According to UHI register $a0 will be set
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to -2 and the FDT address is stored in $a1.
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endmenu
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config SUPPORTS_BIG_ENDIAN
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bool
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config SUPPORTS_LITTLE_ENDIAN
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bool
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config SUPPORTS_CPU_MIPS32_R1
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bool
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config SUPPORTS_CPU_MIPS32_R2
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bool
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config SUPPORTS_CPU_MIPS32_R6
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bool
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config SUPPORTS_CPU_MIPS64_R1
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bool
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config SUPPORTS_CPU_MIPS64_R2
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bool
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config SUPPORTS_CPU_MIPS64_R6
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bool
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config CPU_MIPS32
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bool
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default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
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config CPU_MIPS64
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bool
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default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
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config MIPS_TUNE_4KC
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bool
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config MIPS_TUNE_14KC
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bool
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config MIPS_TUNE_24KC
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bool
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config MIPS_TUNE_34KC
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bool
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config MIPS_TUNE_74KC
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bool
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config 32BIT
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bool
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config 64BIT
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bool
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config SWAP_IO_SPACE
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bool
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config SYS_MIPS_CACHE_INIT_RAM_LOAD
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bool
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config MIPS_INIT_STACK_IN_SRAM
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bool
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default n
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help
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Select this if the initial stack frame could be setup in SRAM.
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Normally the initial stack frame is set up in DRAM which is often
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only available after lowlevel_init. With this option the initial
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stack frame and the early C environment is set up before
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lowlevel_init. Thus lowlevel_init does not need to be implemented
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in assembler.
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config SYS_DCACHE_SIZE
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||
|
|
int
|
||
|
|
default 0
|
||
|
|
help
|
||
|
|
The total size of the L1 Dcache, if known at compile time.
|
||
|
|
|
||
|
|
config SYS_DCACHE_LINE_SIZE
|
||
|
|
int
|
||
|
|
default 0
|
||
|
|
help
|
||
|
|
The size of L1 Dcache lines, if known at compile time.
|
||
|
|
|
||
|
|
config SYS_ICACHE_SIZE
|
||
|
|
int
|
||
|
|
default 0
|
||
|
|
help
|
||
|
|
The total size of the L1 ICache, if known at compile time.
|
||
|
|
|
||
|
|
config SYS_ICACHE_LINE_SIZE
|
||
|
|
int
|
||
|
|
default 0
|
||
|
|
help
|
||
|
|
The size of L1 Icache lines, if known at compile time.
|
||
|
|
|
||
|
|
config SYS_SCACHE_LINE_SIZE
|
||
|
|
int
|
||
|
|
default 0
|
||
|
|
help
|
||
|
|
The size of L2 cache lines, if known at compile time.
|
||
|
|
|
||
|
|
|
||
|
|
config SYS_CACHE_SIZE_AUTO
|
||
|
|
def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
|
||
|
|
SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0 && \
|
||
|
|
SYS_SCACHE_LINE_SIZE = 0
|
||
|
|
help
|
||
|
|
Select this (or let it be auto-selected by not defining any cache
|
||
|
|
sizes) in order to allow U-Boot to automatically detect the sizes
|
||
|
|
of caches at runtime. This has a small cost in code size & runtime
|
||
|
|
so if you know the cache configuration for your system at compile
|
||
|
|
time it would be beneficial to configure it.
|
||
|
|
|
||
|
|
config MIPS_L1_CACHE_SHIFT_4
|
||
|
|
bool
|
||
|
|
|
||
|
|
config MIPS_L1_CACHE_SHIFT_5
|
||
|
|
bool
|
||
|
|
|
||
|
|
config MIPS_L1_CACHE_SHIFT_6
|
||
|
|
bool
|
||
|
|
|
||
|
|
config MIPS_L1_CACHE_SHIFT_7
|
||
|
|
bool
|
||
|
|
|
||
|
|
config MIPS_L1_CACHE_SHIFT
|
||
|
|
int
|
||
|
|
default "7" if MIPS_L1_CACHE_SHIFT_7
|
||
|
|
default "6" if MIPS_L1_CACHE_SHIFT_6
|
||
|
|
default "5" if MIPS_L1_CACHE_SHIFT_5
|
||
|
|
default "4" if MIPS_L1_CACHE_SHIFT_4
|
||
|
|
default "5"
|
||
|
|
|
||
|
|
config MIPS_L2_CACHE
|
||
|
|
bool
|
||
|
|
help
|
||
|
|
Select this if your system includes an L2 cache and you want U-Boot
|
||
|
|
to initialise & maintain it.
|
||
|
|
|
||
|
|
config DYNAMIC_IO_PORT_BASE
|
||
|
|
bool
|
||
|
|
|
||
|
|
config MIPS_CM
|
||
|
|
bool
|
||
|
|
help
|
||
|
|
Select this if your system contains a MIPS Coherence Manager and you
|
||
|
|
wish U-Boot to configure it or make use of it to retrieve system
|
||
|
|
information such as cache configuration.
|
||
|
|
|
||
|
|
config MIPS_INSERT_BOOT_CONFIG
|
||
|
|
bool
|
||
|
|
default n
|
||
|
|
help
|
||
|
|
Enable this to insert some board-specific boot configuration in
|
||
|
|
the U-Boot binary at offset 0x10.
|
||
|
|
|
||
|
|
config MIPS_BOOT_CONFIG_WORD0
|
||
|
|
hex
|
||
|
|
depends on MIPS_INSERT_BOOT_CONFIG
|
||
|
|
default 0x420 if TARGET_MALTA
|
||
|
|
default 0x0
|
||
|
|
help
|
||
|
|
Value which is inserted as boot config word 0.
|
||
|
|
|
||
|
|
config MIPS_BOOT_CONFIG_WORD1
|
||
|
|
hex
|
||
|
|
depends on MIPS_INSERT_BOOT_CONFIG
|
||
|
|
default 0x0
|
||
|
|
help
|
||
|
|
Value which is inserted as boot config word 1.
|
||
|
|
|
||
|
|
endif
|
||
|
|
|
||
|
|
endmenu
|