93 lines
1.9 KiB
C
93 lines
1.9 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
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*/
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#include <common.h>
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#include <linux/arm-smccc.h>
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#include <asm/io.h>
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#include <asm/arch-tegra/pmc.h>
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DECLARE_GLOBAL_DATA_PTR;
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#if IS_ENABLED(CONFIG_TEGRA_PMC_SECURE)
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static bool tegra_pmc_detect_tz_only(void)
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{
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static bool initialized = false;
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static bool is_tz_only = false;
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u32 value, saved;
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if (!initialized) {
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saved = readl(NV_PA_PMC_BASE + PMC_SCRATCH0);
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value = saved ^ 0xffffffff;
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if (value == 0xffffffff)
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value = 0xdeadbeef;
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/* write pattern and read it back */
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writel(value, NV_PA_PMC_BASE + PMC_SCRATCH0);
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value = readl(NV_PA_PMC_BASE + PMC_SCRATCH0);
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/* if we read all-zeroes, access is restricted to TZ only */
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if (value == 0) {
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debug("access to PMC is restricted to TZ\n");
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is_tz_only = true;
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} else {
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/* restore original value */
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writel(saved, NV_PA_PMC_BASE + PMC_SCRATCH0);
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}
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initialized = true;
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}
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return is_tz_only;
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}
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#endif
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uint32_t tegra_pmc_readl(unsigned long offset)
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{
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#if IS_ENABLED(CONFIG_TEGRA_PMC_SECURE)
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if (tegra_pmc_detect_tz_only()) {
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struct arm_smccc_res res;
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arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_READ, offset, 0, 0,
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0, 0, 0, &res);
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if (res.a0)
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printf("%s(): SMC failed: %lu\n", __func__, res.a0);
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return res.a1;
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}
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#endif
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return readl(NV_PA_PMC_BASE + offset);
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}
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void tegra_pmc_writel(u32 value, unsigned long offset)
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{
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#if IS_ENABLED(CONFIG_TEGRA_PMC_SECURE)
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if (tegra_pmc_detect_tz_only()) {
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struct arm_smccc_res res;
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arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_WRITE, offset,
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value, 0, 0, 0, 0, &res);
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if (res.a0)
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printf("%s(): SMC failed: %lu\n", __func__, res.a0);
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return;
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}
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#endif
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writel(value, NV_PA_PMC_BASE + offset);
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}
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void reset_cpu(ulong addr)
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{
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u32 value;
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value = tegra_pmc_readl(PMC_CNTRL);
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value |= PMC_CNTRL_MAIN_RST;
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tegra_pmc_writel(value, PMC_CNTRL);
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}
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